Cadence SH 招聘 Principal PE and Principal Product Validation Engineer

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Cadence SH 招聘 Principal PE and Principal Product Validation Engineer

If you have interest, PLS send your update CV to zhangyl@cadence.com

1. Principal PVS Product Engineer

Position Description:

The Product Engineering team works with Customers and foundries, R&D, Marketing, and the Field Applications Engineers to create products that address the unique and complex needs of our customers. A Physical Verification Product Engineer provides in-depth technical expertise in writing Physical Verification rule decks (i.e. DRC, ERC, FILL and LVS) and the usage of Physical Verification tools throughout physical implementation and signoff verification cycles.

Responsibilities:

Develop Physical Verification rule decks (i.e. DRC, ERC, FILL and LVS)

Setup efficient flows to improve rule deck development quality and product performance.

Run expert-level benchmarks and solve complex customer problems.

Work with the RD, field, customers and foundries to identify and define product requirement and enhancement

Position Requirements:

Knowledge of developing rule decks for commercial physical verification tools (e.g. PVS, Calibre, Hercules, Dracula, Assura, etc.) is required.

Experience in the following areas:

- DRC, includes density, antenna, etc.

- LVS, includes device extraction, parameter measurement, connect/stamp sequences, short isolation, etc.

- Knowledge of netlist formats SPICE, CDL, Verilog, etc.

- DFM, includes yield analysis, via insertion, OPC, FILL, etc.

Experience with layout implementation tools (e.g. Virtuoso, DesignREV, ICStation, etc.) for the creation of qualification cells is required.

Knowledge of automating test suites for the qualification of rule decks is a plus.

Programming of Tcl, Perl, and Skill are a plus

EDUCATION: BS or MS in Electrical Engineering.

2. Principal Product Engineer-----DDR IP

Position Description:

Cadence is looking for an individual to work in design IP team. The group provides configurable DDR memory controller and PHY IP for ASICs. The job will be mainly focused on providing post technical support to customers; however there will be a variety of other engineering tasks that will allow the candidate to expand skills and responsibilities.

Provide technical support to customers for integration of IP into ASICs including:

- Debugging of customers’ simulation or silicon issues.

- Reviewing of customers’ design integration of our IPs.

- Reviewing static timing reports to assist with customers’ timing closure.

- Answering technical questions about IP operation.

- Train field engineers in IP operation.

- Interface with the R&D Team to bridge product improvements and resolve customer issues.

Position Requirements:         

- Excellent oral and written communication

- Good English communication skill

- BS  8+ years of prior work-experience or MS 6+ years of prior work-experience

- All front-end skills – RTL design & verification in Verilog, synthesis, static-timing analysis, DFT

- Back-end skills – place & route, physical verification, timing closure

- Time management skills sufficient to balance multiple high-priority projects.

- Willingness to learn new skills and perform tasks that often go outside area of current expertise.

Additional Desirable Qualifications:

- Experience with Static Timing scripts and report analysis

- Familiarity with DDR memory operation, system applications, AXI, OCP, AHB

- Familiarity with Frame maker

- Scripting – in Perl, TCL, etc..

3. Principal Product Engineer (Location: SH)

Position Description:

1.This employee will work in shanghai Engagement PE team, mainly focus on TSMC-related project.

2.20nm and 16nm FinFET flow establishment, from synthesis to final SI timing closure

3.Work closely with other team members for technique communication and projects. Can take lead role in project plan and action.

4.Co-work closely with R&D team to find the debug the software problem in a IC backend way as early as possible.

Position Requirements:

1.Master with 7-8 years working experience or Bachelor with about 10years experience.

2.IC design background, especially in the back-end flow. Low Power related working experience will be a strong plus.

3.Syntheis, Backend experience, LVS, DRC, CLP knowledge and tape-out experience.

4.Unix System knowledge, vi/TCL/TK/CSH will be plus.

5.Strong scripting capability, including shell/tcl/perl.

6.Good communication in English and Chinese, good confidence and good self-motivation.

7.Good team spirit, well-aligned with the "One Cadence, One Team."

4. Principal PV Engineer for Hierarchical timing flow (Location: SH)

Position Description:

1.This job is an important addition to Encounter quality and performance

2.Responsible for hierarchical flow timing related validation and mainly focus on ILM(Interface Logic Model) related testing

3.Responsible for timing/runtime/memory qualification during flow quality regular review

4.Continuously to add and tune large scale and advance node designs into validation suite

5.Working closely with other team members for technique communication and projects.

Position Requirements:

1.BS with minimum 6~7 years and MS with 4~5 years working experiences. EE background, from design house or EDA company is strong plus.

2.Be familiar with software development process, debugging tools, and configuration management concepts.

3.Excellent knowledge at backend flow in digital design, including placement, optimization, cts, route and SI.

4.Excellent knowledge at timing analysis and some physical sense with hierarchical flow should be a plus

5.Excellent ability to learn, explore and strong ability in solving problems independently

6.Good team working attitude and innovating spirit.

7.Good Chinese and English communication skills.

5.  Principal PV Engineer for Hierarchical physical flow (Location: SH)

Position Description:

1.This job is an important addition to Encounter quality and performance

2.Responsible for hierarchical flow physical related validation and mainly focus on prototyping/floorplaning

3.Responsible to co-work with RnD team closely to maintain reasonable hierarchical physical flow from testing view

4.Working closely with other team members for technique communication and projects.

Position Requirements:  

1.BS with minimum 6~7 years and MS with 4~5 years working experiences. EE background, from design house or EDA company is strong plus.

2.Be familiar with software development process, debugging tools, and configuration management concepts.

3.Excellent knowledge at backend flow in digital design, including prototyping, floorPlan, placement, routing, etc.

4.Some deep physical sense with hierarchical flow will be a plus

5.Excellent ability to learn, explore and strong ability in solving problems independently

6.Good team working attitude and innovating spirit.

7.Good Chinese and English communication skills.