Cadence SH 招聘Staff/Principal SerDes Analog IC Design Engineer

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Title:Staff/Principal SerDes Analog IC Design Engineer

JobDescription:

1.Responsible for the design and development of SerDesanalog/mixed signal IC circuit blocks from initial concept and specificationthrough final verification and conformance to customer requirements.

2.Candidate’s background should demonstrate good problemsolving skills, excellent analog aptitude, good communication skills, andability to work cooperatively in a team environment.  

3.Must have demonstrated experience in SerDes transceiverdesigns including some of the following circuit blocks: System levelmodeling by matlab, C, or VerilogA; Driver; Receiver; Serializer; Deserializerhase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias andBandgap; Voltage Regulators.  

4.Candidate should have working knowledge of a set of commonSerDes standards and their electrical requirements, and a thoroughunderstanding of jitter.

5.Position requires proficiency in using CAD tools forcircuit simulation, layout, and physical verification (Cadence tool experience,lab test experience, and experience at 65nm and below technologies are aplus).  

PositionRequirements:         

1.Master/PHD degree, major in Micro-Electronics, ElectronicEngineering or equivalent

2.Ability to work effectively alone or as well as in a team.

3.Essential that the individual demonstrates strongcommunication, verbal and written

4.Requires good communication skills in English.

5.Industry Experience for at least 8 years for SerDes andHigh Speed silicon mass products

DesirableQualifications:

1.Knowledge of one of key SerDes Analog IC design areas andtheir architectures/applications:

2.Clock Data Recovery; PLL's; Oscillators; Low Noise Design;RF IC building blocks

3.Solid understanding of IC design technology andprocess/methodology in IC design solutions

4.Familiar with Cadence analog and mixed-signal EDA tools isa plus

If you have interest, PLS send your CV to zhangyl@cadence.com

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