This specification covers the I-test and the overvoltage latch-up testing of integrated circuits.
The purpose of this specification is to establish a method for determining IC latch-up characteristics and to
define latch-up failure criteria. Latch-up characteristics are extremely important in determining product
reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to
latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of
these technologies.