Application Engineer----IP (location :SH or BJ)

kengteng

Application Engineer----IP (location :SH or BJ)

If you have interest, PLS send your CV to zhangyl@cadence.com

Responsible for providing pre-sales support and coordinating with the corporate team for post-sales support for Cadence’s Digital Design IP (primarily focused on PCIe/Ethernet, DDRn DRAM and NAND Flash subsystems) within the Asia Pacific (AP) region. Build holistic, value-added design solutions that solve our customer’s problems

Responsibilities include:

1) Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Digital IP solutions for their applications

2) Interface with customer architects and Digital IP business unit to enable evaluation of application specific IP performance and features per customer’s SOC requirements.

2) Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships

3) Providing customer feedback on new/existing requirements for Digital IP usage from customers to the Digital IP business unit.

4) Providing direct technical customer support and assistance to enable customers to successfully integrate/use Digital IP in their SOC.

5) Writing application notes in situation to facilitate customer usage of the IP

Requisite :

1)
Experience in digital design and implementation of controllers/logical sublayers/PCS of Cadence IPs such as PCIe/Ethernet/DDR.

2)
Knowledge of serdes and backend implementation is a plus

3)
Experience with SOC architecture include on-chip fabric (AMBA/Sonics OCP/Arteris NOC), external interconnect protocols (e.g PCIe/Ethernet) and DRAM memory protocols (DDRn, LPDDRn), DRAM PHYs, .NAND Flash (Async, ONFI, Toggle NAND).

4)
Exposure to IP-based SOC design flow and real tape-out experience.

5)
Good written and verbal communication skills and problem solving skills are required.

6)
Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team

7)
Travel within AP region may be required.

8)
Good understanding of the semiconductor IP marketplace and ecosystem is a plus.

If you have interest, PLS send your CV to zhangyl@cadence.com

Responsible for providing pre-sales support and coordinating with the corporate team for post-sales support for Cadence’s Digital Design IP (primarily focused on PCIe/Ethernet, DDRn DRAM and NAND Flash subsystems) within the Asia Pacific (AP) region. Build holistic, value-added design solutions that solve our customer’s problems

Responsibilities include:

1) Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Digital IP solutions for their applications

2) Interface with customer architects and Digital IP business unit to enable evaluation of application specific IP performance and features per customer’s SOC requirements.

2) Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships

3) Providing customer feedback on new/existing requirements for Digital IP usage from customers to the Digital IP business unit.

4) Providing direct technical customer support and assistance to enable customers to successfully integrate/use Digital IP in their SOC.

5) Writing application notes in situation to facilitate customer usage of the IP

Requisite :

1)
Experience in digital design and implementation of controllers/logical sublayers/PCS of Cadence IPs such as PCIe/Ethernet/DDR.

2)
Knowledge of serdes and backend implementation is a plus

3)
Experience with SOC architecture include on-chip fabric (AMBA/Sonics OCP/Arteris NOC), external interconnect protocols (e.g PCIe/Ethernet) and DRAM memory protocols (DDRn, LPDDRn), DRAM PHYs, .NAND Flash (Async, ONFI, Toggle NAND).

4)
Exposure to IP-based SOC design flow and real tape-out experience.

5)
Good written and verbal communication skills and problem solving skills are required.

6)
Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team

7)
Travel within AP region may be required.

8)
Good understanding of the semiconductor IP marketplace and ecosystem is a plus.