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本帖最后由 Annaguo 于 2011-6-15 10:23 编辑
职位：版图设计工程师
工作地点：西安
Job Description:
1.Interface with IC Design/Verification team (timing and power constraints definition)
2.Writing, running, optimization of logic and physical synthesis scripts
3.In-depth knowledge of STA. Ability to handle timing analysis for multiple modes and corners
4.Physical design Floor planning, place & route, clock tree synthesis, routing cleanup
5.Power IR & EM analysis
Parasitic extraction/SPEF/SDF generation
6.Prime Time/ICC STA correlation
7.Formal Verification (Equivalence checking)
8.Physical Verification (DRC, ERC, LVS, ANTENNA)
9.Deep understanding of DSM effects (sub 90 nm experience preferred)
Requirements:
1.Masters/Bachelor’s Degree in Electrical/Electronic Engineering or in related field
2.Synopsys Design Compiler and Power Compiler 3.PERL, TCL languages
4.Prime Time and constraint creation/modification
5.IR analysis tool such as PrimeRail
6.Synopsys ICC experience preferred
7.Calibre and/or Assura
8.Formal Verification tool
9.Knowledge of VHDL or Verilog is a plus
10.RTL Hand-off checks (SpyGlass, UPF) and Design Doc. is necessary
11.Ability to speak and write English is a must, CET 6
12.Self-motivated team player and able to work with minimum supervision
13.Minimum 2 years of physical design and timing closure experience
联系人：郭小姐
电话：0571-28829923
邮箱：guoah@hundsun.com
MSN:annaguo@live.cn |
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发表于 2011-6-15 10:19:45
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