Detecting signal-overshoots for reliability analysis in high-speed SoCs

drjiachen · 发表于 2011-5-21 02:42:34

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

Abstract—The rising level of complexity and speed of SoC
makes it increasingly vital to test adequately the system for signal
integrity. Voltage overshoot is one of the integrity factors that has
not been sufficiently addressed for the purpose of testing and reliability.
Overshoots are known to inject hot-carriers into the gate
oxide and cause permanent degradation of MOSFET transistors’
performance. This performance degradation creates a serious
reliability concern. Unfortunately, accurate parasitic extraction
and simulation to detect the interconnect problems is very time
consuming and very sensitive to the circuit characteristics and
thus is not practical for large SoC.
This paper presents a built-in chip methodology to detect and
measure the signal overshoots occurring on the interconnects of
high-speed system-on-chips. This built-in test strategy does not require
external probing or signal waveform monitoring. Instead, the
overshoot detector cells monitor signals received by a core (e.g.,
from the system bus) and record the occurrence of overshoots over
a period of operation. The overshoot information accumulated by
these cells can be compressed and scanned out efficiently and inexpensively
for final quality grading, reliability analysis, and diagnosis.

Detecting signal-overshoots for reliability analysis in high-speed system-on-chips.pdf (543.17 KB, 下载次数: 63 )