深圳IC Design Engineer

cavell2010

Position: IC Design Engineer
(Location: Shenzhen)
Job Descriptions:
1.Physical design from rtl to netlist; Primarily focus on 90nm/65nm/40nm process technologies and design.
2.Typical tasks include IO-assigning, Floorplan, Clock  generation design, DFT, Static Timing Analysis
Requirements:
.Bachelor Degree or above, Major in electronic engineering or related field.
.Very good experience in one of following area: logic synthesis , static timing analysis, design for testing.
.Experience on script (TCL, Perl, C shell, etc) .
.Dedicated and hard working with good interpersonal and communication skills.
.Good English writing and speaking are required .
.Self motivated to learn new technology and methodology.
职责描述:
1.完成RTL到NETLIST的物理设计; 主要是90纳米、65纳米、40纳米工艺的后端设计。
2.主要设计工作包括IO设计、可测性设计、时钟树生成设计、串绕分析、静态时序分析。
职位要求:
.本科及以上学历，微电子或工程类相关专业
.有很好的综合(synthesis)，静态时序分析(STA)经验，DFT设计经验
.能够熟练使用脚本（TCL,Perl, C shell, etc)
.工作努力、勤奋，具备团队协作精神
.优秀的英语读写能力
.积极进取，优秀的学习能力

ouyds001

想去深圳。。。

standli

which company？

cavell2010

有兴趣的话，可以加我MSN：cavell2010@hotmail.com
或者QQ:1743316785
非常感谢！哈哈！