AMD招聘Design/Design Verification Engineer

Mentos

AMD 上海R&D center现急招以下职位，有兴趣的朋友可以发简历至:
windyy2008@126.com (内部推荐)




Sr. ASIC Design Verification Engineer for Graphics Hardware

Responsibility: Understand the architecture of the chip and functional block being designed Build C/C++ model for simulation Build test bench and monitors for DUT Compose test plan and validation vectors to ensure functional completeness Debug function/performance bugs of graphics chips Preferred Experience: Master graduates from Electrical Engineering (EE) or Computer Science (CS) Familiar with Linux Environment Good written and fluent oral English Experience with design verification methodologies (plus) Major in CS required: 3+ year experience on c/c++ 1+ year experience on Verilog HDL coding and debugging (plus) Familiar with SystemVerilog or SystemC (plus) Major in EE required: 2+ year experience on Verilog HDL coding and debugging 1+ year experience on c/c++ Familiar with SystemVerilog

Sr. ASIC Design Engineer –Power Analysis/Estimation

RESPONSIBILITIES: Develop methodology/flow for different design level power regression at different design stages. Verify design low power features from power perspective. Work closely with the designers to understand design power behavior and optimize design for power. Analyze and estimate design power at different design stages. MINIMUM REQUIREMENTS: MS in EE or related area. 3 years+ experience in ASIC design. Familiar with FE ASIC design flow, low power design knowledge is a plus Experience in function simulation, synthesis, timing analysis. Experience in PTPX/PowerTheater/SPICE is a plus. Strong programming skills in PERL/TCL/SHELL.

MTS of Performance Verification

More than 5 years’ experience with one of following: a) Software: OGL/D3D driver background b) 3D/GPU Architecture c) IC Design/verification Background d) CPU design/verification e) 3D Application programming etc. f) Compiler Back Ground g) Graphics Architecture h) GPGPU related jobs Description of duties in addition to those in job description: - Write test plan for new graphics chips - Write performance tests for new graphics chips - Debug/Analysis performance bugs of graphics chips - Debug function bugs for performance tests - Write performance analysis tools for new graphics chips - Function verification for new features of graphics chips - Write benchmarks for new graphics chips - GPGPU performance verification Preferred Experience: - Master Degree or Above - 5+ year experience on C\C++ - Plus with experience on CPU Design/Verification - Plus with experience on Compiler - Plus with 3+ years’ OpenGL/D3D programming experience - Plus with 3+ years’ OpenGL/D3D driver experience - Plus with 1+ years’ Linux/Shell - Plus with 1+ years’ Perl/Python - Familiar with Graphics Algorithm/Graphics Pipeline - Proficient in English read/write/speaking/listening - Good communication & Team worker

MTS ASIC CAD Engineer

Responsibility:

Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with AMD global teams. Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge graphics processing products Technical support and programming Interface with EDA venders on technology Requirements: Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences Good programming skill with one or more languages (e.g. tcl, perl , python, c/c++, etc) in unix/linux and a strong desire to automate flow Experience in ASIC design (digital design, Front-end and/or Back-end) Familiar with one or more ASIC flows (logic synthesis, STA, formality check, Design for Power, place & route, signal integrity analysis, CTS design, design rule and connectivity verification, DFT ) and usage of related EDA tools Good written and spoken English Good communication skills and be able to work both independently and in a team

Sr. CG/image processing algorithm Engineer

Responsibility:

Parallelize algorithm to leverage advanced feature of AMD platform Implement the paralleled algorithm Tune code performance aggressively with hw and compiler team Requirements: Strong background on CG or image processing algorithm Be good at C/C++ Experienced in algorithm penalization and optimization (a plus) Familiar with linux and scripts(a plus)

Physical Design Engineer

Responsibility:

Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floorplanning, timing closure, place&route, physical verification etc. Requirements: Master and above of EE. Experience on place and routing, signal integrity, power analysis, CTS design, DFT, design rule and connectivity verification, timing closure. Knowledgeable in all aspects of deep submicron ASIC design flow Good listening, writing and speaking English Good communication skills, strong interpersonal skills and the flexibility. Dedicated, hard working and good team player Familiar with Back-End (physical design) EDA tools Familiar with Front-End EDA tools or circuit design is a plus Familiar with Unix/Linux environment and good at scripts

Sr. Physical Design Engineer

Responsibility:

Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. Requirements: PhD with 1+ years of industrial experience or MSEE with 3+ years of industrial experience in ASIC design Expertise in place and routing, signal integrity, power analysis, CTS design, DFT, design rule and connectivity verification, timing closure. Successfully gone through complete product development cycle. Good analytical and debugging skills Good listening, writing and speaking English. Good communication skills, strong interpersonal skills and the flexibility. Dedicated, hard working and good team player Familiar with Back-End (physical design) EDA tools (synopsys,cadence,magma) Familiar with Front-End EDA tools or circuit design is a plus Familiar with Unix/Linux environment and good at scripts

GPU ASIC Integration Engineer

Responsibility:

· Responsible for the execution of the chip integration process. This will include design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design. · Responsible for synthesis, netlist generation, timing and logical equivalency checks, and timing constraint management. In this role you will get to experience many aspects of the chip design process working as the bridge between the logic design & verification group and the physical design group. Every piece of the design that will make it into the final chip will at some point pass through your virtual hands. Requirements: Master Degree in electrical engineering with 4+ years of digital circuit design and logic design experience; Or Bachelor Degree with 7+ years related working experience Familiar with Verilog HDL coding and ASIC Frond-End flow Familiar with unix/linux and scripts (tcl, perl, python etc.) Strong task-based organization skill Computer Architecture and computer Arithmatic (a plus) Computer Graphic Basic knowledge(a plus)

Staff Engineer of Design Verification

Requirements: MS or above of CS, EE or related fields. A solid foundation of Computer Architecture and Operating system At least 5 years work experience on Verification or Design. Proficient on C++ and familiar with Verilog, or proficient on Verilog and familiar with C++ Familiar with Perl or other script language Fluency in English Good at communication

Staff Engineer of Design

Requirements: MS or above of EE or related fields. A solid foundation of Computer Architecture or DDR feature or memory controller At least 5 years work experience on Design. Proficient on Verilog and asic design flow Familiar with Perl or other script language Fluency in English Good at communication Responsibility: a)   Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design b)   Build test bench and monitors for DUT c)   Debug function/perforamcne bugs of relative memory control blocks

wangjunweiair

wangjunweiair

ddddddddddddddddddddd

TomPaul

LZ留的邮箱地址可靠吗？发过简历的说一下啊

armingnet

AMD招人怎么如此强劲啊？呵呵，去年发财了？

Mentos

当然可靠！！！

LZ留的邮箱地址可靠吗？发过简历的说一下啊
TomPaul 发表于 2010-8-25 22:36

                               
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wolfmount

1# Mentos
ok

charlie2010

好强大啊，楼主

Mentos

谢谢大家的简历，会一一联系的

tbb2009

据说有AMD内部的人靠推荐，去年挣了5W+，呵呵。推荐成功的人应该要求和LZ分享一下