Dual-Port RAM 2048*32 (VHDL ,LEF,LIB ,TLF....)

vanduongbk

Key Features

Memory Compiler for Dual Port RAM in 0.35µm CMOS Process (C35/S35) triple metal layout data of memory full read/write capability on each port 65536 bit maximum memory size 8 .. 32 bits per word 128 .. 8192 words per DPRAM Simulation models for 3.3V nominal supply 2 separated or 1 common datain/dataout buses per port tri-state dataout bus

Deliverables

Frontend services (available via Internet) CADENCE cell library with symbol, functional, abstract and msps view TLF 3.0 & TLF 4.3 timing data file LEF file for silicon ensemble SDF annotable Verilog model              VHDL VITAL95 compliant simulation model TLF timing data file for SDF generation LEF file for silicon ensemble              SYNOPSYS cell timing model (interface model)              MENTOR Design Architect symbol QSIM II simulation model & black box desription black box desription                    Backend Services (on order) CADENCE cell library with additional layout view with reduced layout                  data (*)                     gds2 data reduced layout data in gds2 format (*)                     (*) reduced layout data does not contain the following layers:          Diffusion Poly1 N+ Implant P+ Implant Contact

cad14

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blue_man

memory compiler 生成的吗？
这个对别人没有意义。

guoaiying

我看看是什么东西了。

jinzhuzhechixp

但愿这个能用

Desingman

thank you

johnwei

看看，希望不要忽悠我