|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
本帖最后由 robin_li 于 2010-3-31 11:07 编辑
Position: DV Manager
Skills and Experience Requirements
- 10+ years of ASIC design and verification experience with minimum of 3+ years as DV technical lead/architect or manager position.
- Proven experience of the latest design verification methodology such as OVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation, formal checking, power verification, modern design verification tools and languages (e.g. PSL/SVA, SystemC++, SystemVerilog, Vera, Specman, simulation systems)
- In depth experience in use of SystemVerilog and OVM to drive testbench is highly desirable
- In depth knowledge of ASIC design fundamentals from RTL to GDS including DFT verification.
- Working knowledge of x86 assembly programming is an asset.
- Experience in power verification is an asset.
- Verification of Virtualization Components is an asset.
- Proven debugging and problem analysis skills.
- Strong documentation and communication skills.
- Good people and project management skills including scheduling, resource allocation, risk assessment, matrix management, and process development and organized and methodical with proven ability to plan and execute project.
- Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
- Flexible in terms of responsibilities and hours.
大家感兴趣赶快跟我联系吧
E-mail & MSN : milujite@msn.com
|
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2010-3-23 13:39:13
楼主
