上海及深圳急找聘验证工程师及manager，PR（大量）及PR项目经理

dorisyxl

我叫Doris，我是上海KT人才的，我们是一家专业从事IC半导体电子通信的猎头

我们目前在上海急招验证工程师，PR工程师（大量）及项目经理。另在深圳也急招验证经理和工程师。欢迎各位与我联系
Tel: 021-61023600-28
Mobile:135 2465 4976
Email: doris-yu@kthr.com
MSN:doris_yxl@live.cn


1.Senior Physical Design Engineer （若干）

Experience: 5-10 years

Responsible for physical design implementation of complex SoCs Participating in physical design methodologies and flow automation
• Floor plan, place, route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS

Requirements:

BSEE, MSEE preferred 4+ years of experience in block and chip level physical design in 0.13u or 90u technology. Must have successful track record taping out complex chips (min 2M gates) Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, antenna etc.) Prior experience in design timing closure, clock/power distribution and analysis, RC Extraction, place and route. Hands on experience in running static timing analysis (STA) tools like primetime (PT-SI). Circuit level comprehension of time critical paths in the design Should be a power user of P&R and analysis tools from Magma, Cadence or Synapses
• Coding experience in C++, C, Perl and TCL a big plus

2.项目总监 （1人）

岗位职责：
组织IC产品研发，包括确立需求、产品设计、测试工作等；
对研发过程、进度、费用控制进行监督，及时解决研发中的技术难题；
进行团队和项目管理，协调英国公司团队和上海研发中心之间的沟通和合作。

任职要求：
对IC产品设计的技术，方法，流程以及执行有深刻的了解。熟练掌握RTL实现，综合，STA, PrimePower, 对电路的时序问题有着深刻而独特的理解，掌握数字电路后端设计流程以及低功耗设计。
8年以上SOC研发和管理经验，适应工作压力，优秀的团队精神，很强学习能力和组织协调能力，具有强烈敬业精神，具有良好的性格。
具有一定经验的团队领导管理能力，。
善于沟通，并英语流利

3.项目经理 (1)
职责：
负责项目开发，完成从逻辑综合后网表到芯片Tape-out全过程，包括芯片的布局布线，静态时序分析，时序库和物理库的建立，寄生参数提取和物理验证
解决及时解决研发中的技术难题；

要求：
5年以上相关经验
熟悉Cadence,Synopsys或者ｍａｇｍａ　后端工具
熟悉低功耗设计，CTS, padring, top level floorplan, timing closure
有90nm或90nm以下工艺投片经验
unix  使用熟练；
勤奋敬业，沟通能力佳, 英语好。

4.Verification Manager

RESPONSIBILITIES:

- Lead and manage the team that develops the verification environment for USB3
Host/Device/Hubs
- Convert Requirements Documents into Schedule/Resource Plan for team
- Write Test bench and Verification Modules
- Write and Debug Verification Test Cases
- Make tradeoffs between different methodologies and tools to achieve verification requirements
- Create test plans for full chip that includes complex IP
- Design and implement design verification environments
- Code test benches using System Verilog
- Utilize advanced verification tools, formal verification, emulation, and code coverage
- Generate tests and debug the Verilog design


MINIMUM REQUIREMENTS:

- BS in Electrical Engineering or Computer Science, MS preferred
- Minimum of 8 years experience in complex ASIC verification
- 3 years of management experience
- Must be strong in Verilog, Perl/Python and object oriented programming
- Must have excellent communication skills in Mandarin and English


DESIRABLE EXPERIENCE/KNOWLEDGE (should include, however not limited to):
- Directed and Random functional test environment development and use
- Experience with functional/power/performance verification using simulation and emulation environments
- Experience with HW design, simulation, verification, and HW bring-up.

5.IC Verification Engineer/IC 验证工程师

JOB DESCRIPTION:
-To create test plans for both block-level and chip-level according to specification
-To design and implement reusable verification environments and reference model
-To build up test cases and code test benches

QUALIFICATIONS:
- BSEE with minimum 3+year or MSEE with minimum 1-year experience of IC product development
- Proficient in verification language and tools
- Solid knowledge of ASIC design flow
- Familiar with Unix/Linux
- Good scripting skill in Perl / shell / TCL.
- Strong analytical skills, teamwork contributor and excellent communication skills

ilovecolin

check下

gonethewind

我叫Doris，我是上海KT人才的，我们是一家专业从事IC半导体电子通信的猎头

我们目前在上海急招验证工程师，PR工程师（大量）及项目经理。另在深圳也急招验证经理和工程师。欢迎各位与我联系
Tel: 021-61023600-2 ...
dorisyxl 发表于 2010-1-15 15:32

                               
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要求不低啊。。。

g2932026

支持一下

g2932020

不错的工作