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发表于 2011-8-9 12:07:17
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贴一下Abstract，方便大家预览一下内容
Sub-threshold design of CMOS logic circuits is
important for ultra low-power operation. With continuous
scaling of MOS devices to nanometer sizes however,
conventional CMOS logic style may not function properly at
65nm and below due to a variety of leakage currents flowing.
Thus alternative logic styles, such as, transmission-gate, have
been proposed for sub-threshold operation in nanometer
regime. In this work, a new CMOS logic style, that results in
reduced leakage currents both in active and idle modes of
operation leading to a better static and dynamic performance,
is proposed. Simulations have been carried out in Cadence
Spectre to verify the functionality of the gates using standard
65nm technology. Results indicate that static power reduction
of up to 25% has been achieved. The utility of the new logic
style is demonstrated with a 1-bit full-adder circuit. |
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