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Senior Design Engineer for Video Codec
Preferred Experience:
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Major in EE and have Master degree or higher
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3 years beyond working experience on ASIC design
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Must have strong background on video encoding/decoding algorithms
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Must be proficient in Verilog coding, debugging and modeling
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Must be skilled in ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.
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Must be skilled in mainstream EDA tools for design and simulation such as ncsim/vcs, RC/DC, PT, Formality/LEC and DFT.
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Must be familiar with verification methodologies for from block level to SoC level.
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Should be familiar with shell/perl/tcl programming in linux OS.
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Should be familiar with P&R and Manufacture tech.
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Good English hearing, speaking, reading and writing capabilities.
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Will be a big plus if having tape‐out experience.
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Will be a plus if having C/C++, matlab experience
Senior Design Verification Engineer for Video Codec
Preferred Experience:
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Major in CS or EE and have Master degree or higher
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3 years beyond working experience on ASIC design verification
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Must have strong background on video encoding/decoding algorithms
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Must be proficient in C++ programming and debugging in Linux and Windows platforms. Know well about SW engineering.
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Must be experienced in various verification methodologies from block level to SoC level, and familiar with corresponding tools.
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Must be skillful in shell/perl/tcl/Makefile programming in linux OS.
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Should have adequate ASIC design knowledge and be able to debug RTL codes using corresponding tools
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Good English hearing, speaking, reading and writing capabilities.
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Will be a big plus if having tape‐out experience.
工作地点:上海
有兴趣的可MSN联系
rongchris@hotmail.com
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