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知名芯片公司招聘视频类设计验证职位

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发表于 2009-9-2 15:36:39 | 显示全部楼层 |阅读模式

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Senior Design Engineer for Video Codec


Preferred Experience:
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Major in EE and have Master degree or higher
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3 years beyond working experience on ASIC design
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Must have strong background on video encoding/decoding algorithms
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Must be proficient in Verilog coding, debugging and modeling
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Must be skilled in ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.
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Must be skilled in mainstream EDA tools for design and simulation such as ncsim/vcs, RC/DC, PT, Formality/LEC and DFT.
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Must be familiar with verification methodologies for from block level to SoC level.
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Should be familiar with shell/perl/tcl programming in linux OS.
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Should be familiar with P&R and Manufacture tech.
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Good English hearing, speaking, reading and writing capabilities.
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Will be a big plus if having tapeout experience.
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Will be a plus if having C/C++, matlab experience



Senior Design Verification Engineer for Video Codec


Preferred Experience:
-
Major in CS or EE and have Master degree or higher
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3 years beyond working experience on ASIC design verification
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Must have strong background on video encoding/decoding algorithms
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Must be proficient in C++ programming and debugging in Linux and Windows platforms. Know well about SW engineering.
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Must be experienced in various verification methodologies from block level to SoC level, and familiar with corresponding tools.
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Must be skillful in shell/perl/tcl/Makefile programming in linux OS.
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Should have adequate ASIC design knowledge and be able to debug RTL codes using corresponding tools
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Good English hearing, speaking, reading and writing capabilities.
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Will be a big plus if having tapeout experience.


工作地点:上海
有兴趣的可MSN联系
rongchris@hotmail.com

发表于 2009-9-2 22:59:06 | 显示全部楼层
为了挣钱顶楼主
 楼主| 发表于 2009-9-3 10:02:10 | 显示全部楼层
谢谢你了
 楼主| 发表于 2009-9-7 10:29:52 | 显示全部楼层
新的星期,新的开始,大家努力~
发表于 2009-9-7 21:26:49 | 显示全部楼层
day day up


good good study
 楼主| 发表于 2009-9-8 09:38:04 | 显示全部楼层
thank you~
发表于 2009-9-8 11:22:52 | 显示全部楼层
第一个职位要求好高
应该有20W/Y吧?
发表于 2009-9-8 11:24:10 | 显示全部楼层
Must be skilled in ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.

这个,ECO就那个了吧~~~~


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Must be skilled in mainstream EDA tools for design and simulation such as ncsim/vcs, RC/DC, PT, Formality/LEC and DFT.


哎~~~~不会
发表于 2009-9-8 21:53:38 | 显示全部楼层
职位要求好高
 楼主| 发表于 2009-9-10 11:40:02 | 显示全部楼层
呵呵~要求一开始都高的,现在都有一定程度的降低,不过技术方面还是要都会的,只是年限和学历放宽了。
另有一个新的职位急招~
Sr/MTS ASIC Design/Integration Engineer___GNB Project

PREFERRED EXPERIENCE:
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MSEE or PhD and CGPA of 8.0 out of 10.0 or higher with minimum 2-3 years of ASIC design and integration experience is required.
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Familiar with complex high speed ASIC Design process.
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Relevant experience in Graphics, Memory Controller (DDR, DDR2, DDR3), Video, Microprocessor Design, SOC design is a plus.
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Relevant experience in bus protocol USB/PCI/PCIE design is a plus.
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Relevant experience in chip level design/integration, DFT, memBIST, Memory Compiler, STA is a plus.
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Strong logic design, verification and debugging skills.
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Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, and C/C++ programming languages, CMOS transistors and circuits is optional.
-     Good communications skills and ability and desire to work as a team player are a must.


重视integration的能力和经验啊
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