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1>Job Title: Sr. /Jr. ASIC Design Verification Engineer
PREFERRED EXPERIENCE:
- MSEE or PhD and CGPA of 8.0 out of 10.0 or higher are required.
- Familiar with complex high speed ASIC Design process.
- Strong C/C++/System Verilog and HDL/RTL programming skills is a must.
- Relevant experience in Graphics, Memory Controller (DDR, DDR2, DDR3), Video, Microprocessor Design, SOC design and bus protocol PCIE is a plus.
- Strong logic analysis, verification, debugging and problem-solving skills.
- Relevant experience in Design for verification (Assertion Based Verification, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.) is a plus.
- Relevant experience in Hardware emulation, System Performance modeling and analysis is an asset.
- Good communications skills and ability and desire to work as a team player are a must.
2>Job Title:Sr/MTS ASIC Design/Integration Engineer
PREFERRED EXPERIENCE:
- MSEE or PhD and CGPA of 8.0 out of 10.0 or higher with minimum 2-3 years of ASIC design and integration experience is required.
- Familiar with complex high speed ASIC Design process.
- Relevant experience in Graphics, Memory Controller (DDR, DDR2, DDR3), Video, Microprocessor Design, SOC design is a plus.
- Relevant experience in bus protocol USB/PCI/PCIE design is a plus.
- Relevant experience in chip level design/integration, DFT, memBIST, Memory Compiler, STA is a plus.
- Strong logic design, verification and debugging skills.
- Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, and C/C++ programming languages, CMOS transistors and circuits is optional.
- Good communications skills and ability and desire to work as a team player are a must.
3>Job Title:Sr. ASIC Design Engineer for Video/Graphics Post_Processing
PREFERRED EXPERIENCE:
- Minimum BSEE/CE, or equivalent degree.
- 4+ years of verification experience in ASIC product development.
- Strong C/C++ software development experience.
- Experience in Verilog, scripting experience (csh, perl, awk, etc.).
- System Verilog, SystemC and Specman are good assets.
- Knowledge of video/graphics/audio post processing is preferred.
- Knowledge of display protocol such as DP/HDMI/DVI/VGA is big plus.
- Strong problem solving skills, and attention to details.
Good English/Chinese interpersonal skills (verbal and written).
Organized, enthusiastic and self-motivated. Strong interest in hardware verification methodologies.
- Capable of working as an independent contributor and team member.
4>Job Title:Sr. ASIC Design Engineer for Audio Processing
PREFERRED EXPERIENCE:
- Minimum MSEE or equivalent degree.
- Strong C/C++ software development experience.
- Experience in Verilog, scripting experience (csh, perl, awk, etc.).
- System Verilog, SystemC and Specman are good assets.
- Knowledge of video/graphics/audio post processing is preferred.
- Knowledge of display protocol such as DP/HDMI/DVI/VGA is big plus.
- Strong problem solving skills, and attention to details.
- Good English/Chinese interpersonal skills (verbal and written).
- Organized, enthusiastic and self-motivated. Strong interest in hardware verification methodologies.
- Capable of working as an independent contributor and team member.
5>Job Title:Sr. DV Engineer for Video/Graphics/Video Processing
PREFERRED EXPERIENCE:
- Minimum MSEE or equivalent degree.
- Engagement in synthesis and STA timing closure. Synthesis/STA tool knowledge is preferred.
- Exposure in Video/Graphics post-processing domain such as scaling/blending/gamma-correction/2D acceleration.
- Basic knowledge in PD design is preferred, but not mandatory.
- Working knowledge in RTL and gate level simulations.
- Experience on C/C++ is a big plus.
- Strong analytical and problem solving skills along with attention to details.
- Good English/Chinese interpersonal skills (verbal and written).
- Must be self-motivated and able to independently drive tasks to completion.
- Capable of working as an independent contributor and team member
PS:以上职位工作地点均在上海
大家要是感兴趣可以跟我联系哦@_@
E-mail & MSN : milujite@msn.com |
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