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AMD(超威半导体)上海研发中心高薪诚聘南桥芯片相关ASIC设计/验证人才，
薪水待遇优厚，部分人员有出国培训机会
有意者请将中英文简历发送至：
cenarius_2003@yahoo.com.cn
（此为部门内部推荐，优先级高）
公司简介：AMD是世界领先的通用处理器CPU和图形处理器GPU供应商，业务遍及全球。
Sr. Design Engineer-ASIC/Layout
超威半导体（中国）有限公司
公司行业： 电子技术/半导体/集成电路
工作地点： 上海 招聘人数： 若干
工作年限： 二年以上 外语要求： 英语 良好
学 历： 本科
职位描述
DESCRIPTION OF DUTIES:
The AMD South Bridges Group has openings for Design Engineers familiar with a broad range of PC industry I/O
interfaces and system chipset design techniques. The successful candidate will work with team members and apply
his/her design techniques to work on different phases of complex logic design for Southbridge, and chip integration
projects. The role will include working on the following tasks from time to time, specification, HDL coding,
synthesis, DFT assertion, timing closure, etc. The job requires FPGA implementation and debugging of some complex
logic modules, may also need to help the lab PC system bring up or debugging.
PREFERRED EXPERIENCE:
1. The successful candidate will have an MSEE,BSEE or equivalent degree
2. must have minimum of 2~3 years of ASIC design experience, proficient in RTL(verilog), experienced with FPGA,
familiar with simulation, synthesis, and timing. It is preferred if the candidate has network design experience
(ethernet MAC design and PHY interface)
3. It is a plus if the candidate has one or more of the following experience/knowledge, such as PCIE, USB, SATA,
PCI, Embedded Processor (ARM), or Ethernet.
4. Must exhibit good verbal and written communication skills in both Chinese and English.
5. Hands-on lab experience is a plus; able to understand and/or use the use scopes, logic analyzers, has knowledge
or skill of PC system lab debugging.
Sr. Verification Engineer-ASIC/Layout
超威半导体（中国）有限公司
公司行业： 电子技术/半导体/集成电路
工作地点： 上海 招聘人数： 若干
工作年限： 二年以上 外语要求： 英语 良好
学 历： 本科
职位描述
DESCRIPTION OF DUTIES:
The AMD South Bridges Group has openings for a Design Verification Engineer familiar with a broad range of PC
industry I/O interfaces and system chipset verification techniques. The successful candidate will work with team
members and apply current functional verification techniques to improve pre-silicon verification quality and product
Time to Market for Southbridge designs, and chip integration projects. The role will include the delivery of
advanced verification techniques in pseudo-random stimulus generation at unit and system level, DFT feature testing,
testplan creation and implementation. Also, the position will require small portion of time to be spent in our lab
to help with system bring up and debug.
PREFERRED EXPERIENCE:
1.The successful candidate will have an MSEE,BSEE or equivalent degree
2.Must have minimum of 2~3 years of ASIC design verification experience, and has knowledge of design verification
methodologies and object oriented programming.
3.Has knowledge of peripheral I/O interfaces, such as PCIE, USB, SATA,PCI or Ethernet. Experience with C++, Verilog
design and simulation is a must, testbench creation and functional coverage with HVL's such as System Verilog or
SystemC is a plus, as is experience with formal verification tools.
4.Must exhibit good verbal and written communication skills in both Chinese and English.
5.Hands-on lab experience is a plus; able to understand and use scopes, logic analyzers, has knowledge and skill of
PC system lab debugging, small board alternation. |
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发表于 2009-7-2 00:14:30
