Introduction to Embedded System Design Using Field Programmable Gate Arrays

silvia

嵌入式系统设计 图书.

silvia

目 录
1 Introduction....................................................................................................... 1
1.1 Embedded System Overview..................................................................... 1
1.2 Hypothetical Robot Control System .......................................................... 2
1.3 Digital Design Platforms ........................................................................... 4
1.3.1 Microprocessor-based Design ........................................................ 5
1.3.2 Single-chip Computer/Microcontroller-based Design.................... 7
1.3.3 Application Specific Standard Products (ASSPs)........................... 8
1.3.4 Design Using FPGA..................................................................... 10
1.4 Organization of the Book......................................................................... 12
Problems ...........................................................................................................14
References ………………………………........................................................15
Further Reading………………….. .................................................................. 16
2 Hardware Description Language: Verilog.................................................... 17
2.1 Software and Hardware Description Languages...................................... 17
2.2 Let’s Use Verilog as Our HDL!............................................................... 19
2.3 Design Examples Using Verilog.............................................................. 19
2.3.1 Gate Level Model ......................................................................... 20
2.3.2 Combinational Circuits Using Data Flow Modelling ................... 21
2.3.3 Behavioural Logic ........................................................................24
2.3.4 Finite State Machine (FSM) ......................................................... 27
2.3.5 Arithmetic Using HDL................................................................. 35
2.4 Pipelining…… . .......................................................................................40
2.5 Module Instantiation and Port Mapping .................................................. 40
2.6 Use of Pre-designed HDL Codes............................................................. 45
2.7 Simulating Digital Logic Using Verilog.................................................. 47
2.7.1 EDA Tool Flow for Simulation .................................................... 47
2.7.2 Creating a Test Bench for HDL-based Digital Logic ................... 49
2.7.3 Post Place and Route Simulation.................................................. 49
2.7.4 Simulation of Algorithm Using Pre-designed Codes.................... 51
Problems ...........................................................................................................51
Further Reading………………….. ..................................................................51
3 FPGA Devices.................................................................................................. 53
3.1 FPGA and CPLD..................................................................................... 53
3.2 Architecture of a FPGA........................................................................... 54
3.2.1 FPGA Interconnect Technology................................................... 54
3.2.2 Logic Cell .....................................................................................56
3.2.3 FPGA Memory .............................................................................61
3.2.4 Clock Distribution and Scaling..................................................... 67
3.2.5 I/O Standards................................................................................70
3.2.6 Multipliers .................................................................................... 71
3.3 Floor Plan and Routing ............................................................................ 72
3.4 Timing Model for a FPGA....................................................................... 74
3.5 FPGA Power Usage................................................................................. 75
Problems ...........................................................................................................79
Further Reading……………. ...........................................................................80
4 FPGA-based Embedded Processor................................................................ 81
4.1 Hardware–Software Task Partitioning..................................................... 81
4.2 FPGA Fabric Immersed Processors ......................................................... 82
4.2.1 Soft Processors .............................................................................82
4.2.2 Hard Processors ............................................................................84
4.2.3 Tool Flow for Hardware–Software Co-design ............................. 84
4.3 Interfacing Memory to the Processor....................................................... 85
4.4 Interfacing Processor with Peripherals .................................................... 86
4.4.1 Types of On-chip Interfaces ......................................................... 88
4.4.2 Wishbone Interface.......................................................................89
4.4.3 Avalon Switch Matrix .................................................................. 90
4.4.4 OPB Bus Interface........................................................................90
4.5 Design Re-use Using On-chip Bus Interface ........................................... 92
4.6 Creating a Customized Microcontroller................................................... 94
4.7 Robot Axis Position Control.................................................................... 98
Problems .........................................................................................................100
References…………………...........................................................................101
Further Reading……………. .........................................................................101
5 FPGA-based Signal Interfacing and Conditioning .................................... 103
5.1 Serial Data Communication................................................................... 103
5.2 Physical Layer for Serial Communication ............................................. 106
5.2.1 RS-232-based Point-to-Point Communication ........................... 106
5.2.2 RS-485-based Multi-point Communication................................ 106
5.3 Serial Peripheral Interface (SPI) ............................................................ 109
5.4 Signal Conditioning with FPGAs .......................................................... 111
Problems .........................................................................................................113
References…………………….......................................................................114
Contents xiii
6 Motor Control Using FPGA......................................................................... 115
6.1 Introduction to Motor Drives ................................................................. 115
6.2 Digital Block Diagram for Robot Axis Control..................................... 115
6.2.1 Position Loop.............................................................................. 116
6.2.2 Speed Loop.................................................................................117
6.2.3 Power Module ............................................................................118
6.3 Case Studies for Motor Control ............................................................. 119
6.3.1 Stepper Motor Controller............................................................ 119
6.3.2 Permanent Magnet DC Motor .................................................... 122
6.3.3 Brushless DC Motor ................................................................... 125
6.3.4 Permanent Magnet Rotor (PMR) Synchronous Motor ............... 126
6.3.5 Permanent Magnet Synchronous Motor (PMSM)...................... 131
Problems .........................................................................................................135
Further Reading……………..........................................................................136
7 Prototyping Using FPGA ............................................................................. 139
7.1 Prototyping Using FPGAs ..................................................................... 139
7.2 Test Environment for the Robot Controller ........................................... 142
7.3 FPGA Design Test Methodology........................................................... 143
7.3.1 UART for Software Testing ....................................................... 143
7.3.2 FPGA Hardware Testing Methodology...................................... 144
Problems .........................................................................................................151
References…………………...........................................................................152
Index .................................................................................................................... 153

silvia

封面, 如何将封面直接显示?

gina.g

thanks

yzaichao

正在找这个

bithxm

真是本好书呀

kentlin77

good good good good good good

vineeth

thanks for sharing

vineeth

very useful...........

palakaran

thanks    you