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[原创] FPGA应用心得:用VHDL设计任意频率的分频器

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发表于 2006-3-14 10:15:02 | 显示全部楼层 |阅读模式

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本帖最后由 cjsb37 于 2013-4-29 09:11 编辑

Sometimes I need to generate a clock at a lower frequency than the main clock driving the FPGA. If the ratio of the frequencies is a power of 2, the logic is easy. If the ratio is an integer N, then a divide-by-N counter is only a little harder. But if the ratio isn't an integer, a little (and I mean a little) math is required.

Note that the new clock will have lots of jitter: there's no escaping that. But it will have no drift, and for some applications that's what counts.

If you have a clock A at frequency a, and want to make a clock B at some lower frequency b (that is, b < a), then something like:




d = 0;
forever {
  Wait for clock A.
  if (d < 1) {
    d += (b/a);
  } else {
    d += (b/a) - 1;             /* getting here means tick for clock B */
  }
}


but comparison against zero is easier, so subtract 1 from d:




d = 0;
forever {
  Wait for clock A.
  if (d < 0) {
    d += (b/a);
  } else {
    d += (b/a) - 1;             /* getting here means tick for clock B */
  }
}


want an integer representation, so multiply everything by a:




d = 0;
forever {
  Wait for clock A.
  if (d < 0) {
    d += b;
  } else {
    d += b - a;                 /* getting here means tick for clock B */
  }
}


For example. I just bought a bargain batch of 14.1523MHz oscillators from BG  but I need to generate a 24Hz clock.

So a=14152300 and b=24:




d = 0;
forever {
  Wait for clock A.
  if (d < 0) {
    d += 24;
  } else {
    d += 24 - 14152300;                 /* getting here means tick for clock B */
  }
}


For a hardware implementation I need to know how many bits are needed for d: here it's 24 bits to hold the largest value (-14152300) plus one more bit for the sign. In VHDL this looks like:




signal d, dInc, dN : std_logic_vector(24 downto 0);
process (d)
begin
  if (d(24) = '1') then
    dInc <= "0000000000000000000011000";    --  (24)
  else
    dInc <= "1001010000000110110101100";    --  (24 - 14152300)
  end if;
end process;
dN <= d + dInc;
process
begin
  wait until A'event and A = '1';
  d <= dN;
  -- clock B tick whenever d(24) is zero
end process;







发表于 2006-3-15 08:02:49 | 显示全部楼层

FPGA应用心得:用VHDL设计任意频率的分频器

谢谢,收下了
发表于 2006-10-21 15:01:58 | 显示全部楼层
呵呵
好东西呀
发表于 2006-10-27 13:58:57 | 显示全部楼层
谢谢楼主共享
发表于 2006-12-18 21:33:19 | 显示全部楼层
FPGA应用心得:用VHDL设计任意频率的分频器


谢谢,
发表于 2007-3-28 09:47:11 | 显示全部楼层
太好了,谢谢楼主!!!
发表于 2007-5-23 07:33:31 | 显示全部楼层
great!!!
i just need the code.
发表于 2007-5-24 11:02:15 | 显示全部楼层
xia ok  太好了,谢谢楼主!!!
发表于 2007-5-29 23:57:13 | 显示全部楼层
谢谢楼主了
发表于 2007-6-3 11:09:18 | 显示全部楼层
:D
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