vcs2018/2020/2022运行报错

xcq838587

vcs2018/2020/2022运行报错，这个是软件安装好系统自带的demo，O-2018.09-SP2/doc/examples/basic-hdl/verilog/syn_fifo
license是使用ocad大神生成的，破解是1path破解的，测试2018.09，2020.12，2022.06都是一样的报错
#make all
\rm -rf simv* csrc* *.log
/soft/synopsys/vcs/O-2018.09-SP2/bin/vcs fifo.v tb_fifo.v +v2k -debug_access+pp+f  -l comp.log
                         Chronologic VCS (TM)
       Version R-2020.12-SP1_Full64 -- Sun Oct 20 06:14:39 2024

                    Copyright (c) 1991 - 2021 Synopsys, Inc.
   This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction,
            or distribution of this software is strictly prohibited.

Parsing design file 'fifo.v'
Parsing design file 'tb_fifo.v'
Top Level Modules:
       tb_fifo
No TimeScale specified
Starting vcs inline pass...

1 module and 0 UDP read.
recompiling module tb_fifo
make[1]: Entering directory `/home/xucq/syn_fifo/csrc'
make[1]: Leaving directory `/home/xucq/syn_fifo/csrc'
make[1]: Entering directory `/home/xucq/syn_fifo/csrc'
rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
if [ -x ../simv ]; then chmod a-x ../simv; fi
g++  -o ../simv      -rdynamic  -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-rpath=./simv.daidir -Wl,-rpath=/soft/synopsys/vcs/R-2020.12-SP1/linux64/lib -L/soft/synopsys/vcs/R-2020.12-SP1/linux64/lib  -Wl,-rpath-link=./  /usr/lib64/libnuma.so.1   objs/amcQw_d.o   _810_archive_1.so  SIM_l.o      rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o           -lvirsim -lerrorinf -lsnpsmalloc -lvfs    -lvcsnew -lsimprofile -luclinative /soft/synopsys/vcs/R-2020.12-SP1/linux64/lib/vcs_tls.o   -Wl,-whole-archive  -lvcsucli    -Wl,-no-whole-archive        _vcs_pli_stub_.o   /soft/synopsys/vcs/R-2020.12-SP1/linux64/lib/vcs_save_restore_new.o /soft/synopsys/verdi/R-2020.12-SP1/share/PLI/VCS/LINUX64/pli.a -ldl  -lc -lm -lpthread -ldl
../simv up to date
make[1]: Leaving directory `/home/xucq/syn_fifo/csrc'
CPU time: .620 seconds to compile + .519 seconds to elab + .344 seconds to link
simv -l run.log
make: simv: Command not found
make: *** [run] Error 127

test_alan

必须赞一个，这个解法有点意思，看起来那段不重要的代码是在防xxx(懂的都懂）

linkman2

Thank you!

bzwang

thanks

tracy6969

   

xcq838587 发表于 2024-10-20 23:52
patcher.py，这个怎么使用，使用方法是啥  pather.py 目录

usage: ./patcher.py /path/to/library.so

xcq838587

问题已解决，测试VCS2020.12已可以正常跑，通过pather.py  vcs/R-2020.12-SP1/linux64/lib/libvcsnew.so，感谢万能的坛友，也感谢pather.py提供者，
https://github.com/mperov/fixSegfaultVCS

xcq838587

   

xcq838587 发表于 2024-10-20 23:52
patcher.py，这个怎么使用，使用方法是啥  pather.py 目录

./patcher.py linux64/lib/libvcsnew.so

xcq838587

   

tracy6969 发表于 2024-10-20 21:56
thanks, have you tried provided automatic way with patcher.py ?

patcher.py，这个怎么使用，使用方法是啥  pather.py 目录

tracy6969

   

xcq838587 发表于 2024-10-20 18:05
https://github.com/mperov/fixSegfaultVCS
有人使用这个方法，但是 hexedit /eda/synopsys/vcs/Q-2020.03/ ...

thanks, have you tried provided automatic way with patcher.py ?

xcq838587

https://github.com/mperov/fixSegfaultVCS
有人使用这个方法，但是 hexedit /eda/synopsys/vcs/Q-2020.03/linux64/lib/libvcsnew.so，不知道怎么修改