Chip Power Architect

梁山伯与猪硬来

微信：thomas-44444444
上海,深圳,北京  

- Use cases definition. Benchmark and scope the workload of different use cases.​
- Work closely with cross functional teams such as design, performance, product, firmware, etc.; Provide solution and tradeoff to converge on key design decisions.​
- Power estimation of future silicon designs. Ability to create a power model from scratch based on high level feature descriptions and to modify/calibrate the pre & post-silicon power model of an existing design.​
- Design Mixed-Signal Cross-Domain Closed-Loop Controllers for Accelerated Computing Power Management Systems.
- Integrate common implementation across features such as DVFS Management.
- Help define requirements and specifications to vendors to design required ICs/components
职位要求
- PHD/MS degree in Computer Engineering or Computer Science. ​
- 7+ years of relevant power architecting experience. ​
- Knowledgeable in power management techniques such as voltage/frequency scaling, leakage reduction, and power throttling.
- Experience in end-to-end ASIC design methodology such as silicon process, RTL design and verification, synthesis, floorplanning, timing closure, packaging, etc. Prior participation in a successful IP or SoC projects is highly preferred.​
- Familiar with board level design features such as power tree, voltage regulation, thermal solution, etc. ​
- Working Knowledge of SMPS, LDO, digital controller.
- Modelling with Spice/Python or equivalent, and proficient with Verilog and C/C++
- General Understanding of ASIC Productization: ATE, Binning, Voltage-Margining, etc.
150万预算以上