验证主管
Job Responsibilities:
Work with designer to get a full deep insight on the design and develop stressful test plan
Build test bench and create testcase to ensure test coverage
Run simulation in both RTL and netlist level, debug and fix issues, create test reports
Run regression test for each design (RTL/Netlist) update
Develop verification IP which can be reused at different level verification
Co-work with FPGA engineer to prepare test vector, support test and debug