DRV与SSO

能吃不想胖

现在只知道DRV测的是驱动能力，sso测的是抗干扰能力，但是在实际仿真中。公司前辈说完先仿真drv，找到一组大于vsply_high得值，付给IO的ds0  ds1  ds2  ds3，跑sso。有大佬能讲一下他俩的仿真流程和关系吗？

peterlin2010

SSO= Simultaneous Switch OUTPUT Noise 同步开关输出噪声  ?
https://resources.system-analysi ... ng-output-sso-noise

The Cause of SSO Noise

Every IC contains banks of input and output pins, and connections between necessary pins need to be routed across a PCB to form interconnects. The IC and PCB both contain parasitics due to their layout and construction, and these factors combine to produce SSO noise when an output CMOS buffer switches. When the gate regions in the CMOS buffer switch states (output goes from HIGH to LOW), a strong burst of current flows through the IC die and into the ground plane.

The image below shows a familiar schematic, where the CMOS buffer switches states and produces a strong current draw through the die ground and into the PCB ground plane. The connections made to the PCB ground plane have some parasitic inductance, and the trace connecting the driver and receiver have some parasitic capacitance(input and output capacitances plus trace capacitance).

Circuit schematic showing how SSO noise arises due to parasitic capacitance in the I/O pins and parasitic inductance in the bond wire, lead frame, via, and the PCB ground plane.

When these parasitics are combined with the on-state resistance of the bottom NMOS transistor, an RLC circuit is formed, which can exhibit an underdamped oscillation. This underdamped oscillation circulates from the signal ground pin and through the die ground/PCB ground. This oscillation modulates the LOW state voltage as measured with respect to the ground plane.

In effect, the ground plane potential has been momentarily increased due to switching as measured against the I/O pin, and the fluctuation falls back to zero with underdamped response. This oscillation due to ground bounce only appears on the HIGH to LOW transition in a switching CMOS buffer.

SSO Noise in High Pin Count ICs

A single CMOS buffer switching with ~10 ns rise time with 50 mA output and ~10 nH total parasitic inductance will only exhibit ~50 mV peak ground bounce. For 3V3 and 1V8 components, this is completely tolerable; a single CMOS bufferwill still output a sufficiently stable digital signal while staying within the receiver’snoise margin. For a slow protocol like SPI (300 ns rise time), ground bounce is totally unnoticeable.

The problem comes from working high gate count chips. When one I/O switches from HIGH to LOW, the ground potential rise is superimposed on all other outputs that share the same ground reference in the IC. When more I/O buffers switch simultaneously, the total shift in the ground potential is larger.

This situation is shown below for an arrangement of four buffer circuits. At a specific clock instance, the bottom-right buffer is switching from LOW to HIGH, while the other buffers are simultaneously switching from HIGH to LOW. When this happens, the three HIGH-to-LOW switching buffers shift the ground plane potential, which induces simultaneous noise on the output of the LOW-to-HIGH switching buffer. For the LOW-to-HIGH buffer, SSO noise is now seen on the rising edge because the remaining buffers in this arrangement are making a HIGH-to-LOW transition.

SSO noise due to multiple buffers switching simultaneously.

Reducing SSO Noise

The causes of SSO noise in a PCB are related to parasitic inductance in the IC/PCB and the total resistance present in the current loop shown in the above figure. The principle methods for reducing SSO noise are as follows:

•        
  Use components that require series termination. This only applies to single-ended signalling standards without internal pullup/pulldown resistors for termination. Placing a series terminator, as well as reducing parasitic inductance, can provide enough damping to overdamp any oscillation due to SSO noise.
•        
  Increase the parasitic capacitance in the trace and I/O pin. This is one of the effects of adding a bypass capacitor. The other way to do this is to opt for wider traces, but this will require thicker laminate layers when the PCB requires impedance controlled routing.
•        
  Reduce parasitic inductance in the ground connection. This will have a dual effect in your combating SSO noise. First, it will reduce the magnitude of the ground potential shift when SSO noise occurs. Second, it will bring the transient response closer to the overdamped regime. This is done by using flip-chip components instead of bond wire components. You can also cut the ground via inductance in half by using two vias in parallel.
  
  

Note that power bus ringing or droop and SSO noise can both occur in a PCB layout, and it is not so easy to distinguish these when they occur simultaneously. These two effects will always occur in your PCB, but your goal as a designer is to ensure they are minimized so that they will not cause signal integrity problems for your components. Just like designing for low SSO noise, the parasitics in a PDN also need to be tailored, albeit to produce ultra-low impedance on the PDN.

Integrated simulation tools can help you analyze your circuit designs and your PCB layout to prevent SSO noise. Power integrity and signal integrity are disturbances that will continue to confound and effect designs, ensuring that you have the capacities and tools to simulate, analyze, and model appropriately will give you the necessary step-up in moving forward.

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Simultaneous Switch Noise同步开关 ，简称为SSN  

同步开关噪声(SSN)是由IO 输出缓冲同时开关产生的，也被称作同步开关输出噪声(SSO)。产生SSO 的一个主要原因是电源分配系统(PDS)存在阻抗

peterlin2010

ANSYS SIwave教學> Simultaneous Switching Noise            

   https://www.oldfriend.url.tw/SIwave/ansys_ch_ssn.html