通过uvm_hdl_force操作多bit wire信号的局限问题

taoqing

从下图中分别贴出code和仿真log信息，发现通过对于多bit wire型信号，只想通过uvm_hdl_force操作wire信号的第6bit，但是会报错误，而实验发现多bit reg型信号却是可以操作某单bit的，搞不懂为啥reg型信号和wire型信号会有这个区别？

sfc19910705

ERROR: VPI NOFORCB: vpi_put_value() cannot force a
bit of an unexpanded vector net
Some of the verilog simulation will not expand out the output bus, so you
cannot use .input/.output/.inout to drive the signal.
For the output [MSBSB] name that is causing the issue, add "wire scalared
[MSBSB] name". Alternatively, you can set the signal as "output reg".

sfc19910705

ERROR: VPI NOFORCB: vpi_put_value() cannot force a
bit of an unexpanded vector net
Some of the verilog simulation will not expand out the output bus, so you
cannot use .input/.output/.inout to drive the signal.
For the output [MSBSB] name that is causing the issue, add "wire scalared
[MSBSB] name". Alternatively, you can set the signal as "output reg".

ppeezz

uvm_hdl_*系列函数各家EDA公司的实现是不同的，所以如果想要找到wire和reg的原因，可能需要去trace simultor的vpi函数。
不过对于你上述的验证要求，你是否可以采用先uvm_hdl_read multi-bit reg/wire，然后modify对应的bit，最后uvm_hdl_force multi-bit的方式实现。

季候风一号

这楼主我肯定认识

saipolo

uvm_hdl_force这个DPI底层是VPI的vpi_put_value实现的，可以看看vpi_put_value这个函数使用的限制，绕过限制，用其他方式实现。