Power OK电路设计问题

victor0o0

andy2000a 发表于 2020-7-15 16:46
如何判断 bandgap ready  ?  用 mosVth ??   有没不需 bandgap 的 power_ok , 因电路不只一组 power  .  ...

bandgap的ready信号看具体结构，一般情况下bandgap没启动的时候里面的运放工作状态可以作为指示

田宗艳

学习了

jeffej

add some delay for por signal

camelotking

andy2000a 发表于 2020-7-13 10:44
power ok电路是不是可以用POR来做-->  电路本身有 por  大约 0.8v 左右 纯就给 digitalpower_on rest ., 但 ...

Actually, these 2 circuit have different purpose. The VCCOK from UVLO is used to power down/up the analog or bias circuit and POR is used to reset the digital kernel. A lot of chips use digital core as timing and sequence controller.
Before power supply is applied, there is a circuit consuming tiny current to maintain a enable circuit. Once the chip is enabled, the internal LDO will be turned on and VCC UVLO will start detecting VCC with threshold. Once VCC is higher than the threshold, VCCOK will be high.

You don't want to reset the digital core as VCC is not ready. As I mentioned, the digital circuit may control timing, sequence and auto-calibration. If VCC is not OK, these steps may cause false alarm or results.

POR (active high) should maintain high after VCCOK=high for a certain period to guarantee the digital core fully reset.

andy2000a

最后 用 mos vth 做简单power_ok . 不是很准, 但 ,简单就好.

主要有 2 组电源.  Vcore   and 模拟vdd ,  模拟vdd 一组有 bandgap  的 pok比较准,

但麻烦在  vcore 跟模拟vdd 电 都外给 , 系统端何时来电给 CHIP 完全无法控制.

Vcore 如果没 pok, 我是怕低电压下digital会乱动.

偏偏要求省电 模拟端全给 digital 控制. 否则, 原来是想模拟端做power_ok 电路.
判断 vdd 认为 ready , vcore 也由模拟端判断都 ready , 通知digital 后chip 才开始工作.
但后来要求模拟端 全 off , 连 bandgap 都要关 .