已建立一个vhdl文件和testbench波形源文件(已经设置好输入仿真波形),当声称预期输出响应时报错,如下
Launching Application for process "Generate Expected Simulation Results".
Reading d:/xilinx/tcl/vsim/pref.tcl
# 5.8c
# do wave.ado
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity fourbitscount
# -- Compiling architecture behavioral of fourbitscount
# Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity wave
# -- Compiling architecture testbench_arch of wave
# -- Loading entity fourbitscount
# -- Compiling configuration fourbitscount_cfg
# -- Loading entity wave
# -- Loading architecture testbench_arch of wave
# vsim -lib work -t 1ps wave
# Licensing checkout error with feature xe-starter. (Error code -9.)
# The hostid of the license does not match the hostid for this machine.
# One of the following is likely:
# -The license is intended for another machine.
# -A dongle is not plugged into this machine.
# -The dongle driver is not installed or is not functioning properly.
# -The hostid mechanism has been changed or removed from this machine.
# ** Error: Failure to obtain a VHDL simulation license.
# Error loading design
Error loading design
ERROR: VSim failed to simulate annotated testbench
请问是什么原因,谢谢!