我的机子系统是 Ubuntu 16.04, 安装了 vcs K-2015.09_Full64 版本。工程是Verilog + C混合的代码。compile 和elaborate都没问题,在执行simv文件时,报如下错误:Error-[SC_RTG] Incorrect usage of Runtime Generics
Using Runtime Generics to change design hierarchy is not supported due to one of following reasons:
You are running partition compilation flow.
GEN_CODE_FOR_ALL is not set to TRUE in synopsys_sim.setup.
Please correct the cause and recompile your design.