世界级通信芯片商诚招Sr. Engineer (SoC/HW - VLSI/Validation SDC)，地点：上海

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世界级通信芯片商诚招Sr.Engineer (SoC/HW - VLSI/Validation SDC)，地点：上海，如有兴趣，欢迎添加微信：taiyanqian或QQ：970890075了解详细的信息。

Responsibilities                 

-Interfacing with the design teams toensure DFT design rules and guidelines are met

-Verification of ATPG test patterns for(SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models

-MBIST verification and test patterngeneration through Mentor tool

-Work closely with design team on IDDQconstrains validation

--Work with design team on functional DFTtest pattern generation and simulation

-Simulating and verifying the ATPG (SAF,TDF) and MBIST patterns on unit delay and min/max timing corners

-Work with QVPS team on the test vectorsimulation and delivery

-Work with Test Engineers to debug/diagnosemanufacturing defects

-Maintain existing DFT verificationenvironments

-Developing, enhancing and maintainingscripts as necessary

Basic Qualifications          Required:

5+ years ASIC/DFT and various aspectssimulation, Silicon validation or similar education/experience equivalent

Preferred:

-Detailed knowledge on DFT concepts,pattern simulation, Silicon debug

-JTAG, MBIST, Scan Compression, ATPG, FaultSimulation and at-speed testing

-Rich experience with analog test, such asPLL, ADC, DAC, PHY PRBS testing

-Rich experience with gate level simulation

-Rich experience with UVM

-Excellent problem solving skills

-Experience with one or more scriptinglanguages(Perl/TCL) is desired

-Strongwritten and verbal communication skills

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