谱瑞集成电路(上海) digital/logic verification engineer

vivikinghjf

职位：Digital Verification Engineer
RESPONSIBILITIES:
- Develop and execute verification plan
- Develop and maintain verification environment from unit level to system level
- Define and implement functional/code coverage plan
- Code/functional coverage analysis
- Responsible for running both RTL & gate level simulation
- Develop testing and regression methodologies for new verification flow
- Develop/maintain/enhance environment tools/scripts/makefiles

REQUIREMENTS: - Familiar with hardware verification language(Vera, Specman-E, SystemC, SystemVerilog), SystemVerilog is a strong plus

- Experienced in UVM is preferred
- Proficient and experienced with the C/C++ program
- Experience in ASIC design or verification
- Proficient with Verilog HDL - Proficient with one or more scripting languages, such as Shell, Perl and TCL
- Familiar with logic simulators and debug tools (VCS, NC-Verilog, Verdi etc)
- Experience with Verilog PLI is a plus
- Master degree in Electrical Engineering/Computer

说明：公司介绍请看中国IC设计十佳No.1:http://laoyaoba.com/wordpress/?p=4209

职位要求：职位要求并没有硬性的规定。

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