MTS for ASIC verification engineer

RecruiterAMD

MTS for ASIC verification engineer

Pls. send your resume to maggie1.zhang@amd.com if you’reinterested in our position.

AMD System Management Unit(SMU) IP team deliversdifferentiated system management IP for all AMD products. You'll be workingwith the global team on complicated clock scheme, security processing, networkon chip, power management, etc.

Requirement:

* candidate is preferred to be MSEE with minimum of 5 years,or BSEEwith minimum of 7 years experience indigital ASIC/SOC designverification.

* deep understanding on ASIC/SOC design flow

* Excellent knowledge ofdesign verification methodology,such as VMM or OVM and UVM.

* Solid experiences with simulation model creation and thetestbench build

* Strong SystemVerilog experiences.

* Be good at scripting language, such as Perl, Cshell, Ruby,and Makefile.

* C/C++ software development experiences is a plus

It is a must that the candidate has one or more of thefollowing experience/knowledge, such as X86/ARM/8051 architecture,AMBA(AXI/AHB/APB)bus, low power design, clock generation and control, LegacyIPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs(I2S/I2C/UART), JTAG,etc.

The candidate is expected to exhibit good verbal and writtencommunication skills in both Chinese and English, specialized knowledge plusbroad technical knowledge that facilitates integrative thinking, drivingexecution of qualityand timely result, capability to solve complex, novel andno-recurring problems and decision-making on critical technical areas.

Responsibility:

* Work with designer to get a full deep insight on thedesign under test

* Develop stressful testplan

* Build testbench

* Create testcase to ensure maximum coverage

* Develop verification IP which can be reused at differentlevels of verfication: block level, sub-system level, SoC level, etc.

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