Cadence招聘Principle/Lead Verification Engineer (数字前端验证)

kengteng

Cadence招聘Principle/Lead Verification Engineer (数字前端验证)

Location： SH

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Position Description:

Deliver/implementadvanced verification solutions by utilizing Cadence’s Incisive Verificationproduct portfolio. The engineer should be able to act as a strong team memberand contributor, leading team projects and initiatives. Exercise judgmentwithin generally defined practices and policies.

Specificduties include:

-- Deepunderstanding on ASIC/SOC design flow

-- Excellentknowledge of advanced verification methodology like eRM/OVM/UVM

-- Familiarwith Cadence’s Incisive Plan to Closure Methodology (IPCM)

--Proficiencyin System Verilog,  System C and/or e(Specman)

-- Developingand using Verification Components (eVC, OVC, UVC, VIP)

-- Developingand using assertion based verification and formal analysis methods

--Skilledin scripting language, such as Perl, C shell, Makefile

-- Assessingthe project verification requirements

-- Operatingin a lead role regarding architecting and implementation of project   

     verification environment/solution.

-- Maycoordinate/lead others within the scope of a defined project

  Position Requirements:

-- Musthave BS degree with 10+ years of applicable experience, MS degree with 7+ yearsof applicable experience in electrical engineering, microelectronics,comparable engineering science or solid state physics. Essential that the individualdemonstrates strong communication, verbal and written. Requires goodcommunication skills in English.

Desirable Qualifications:

-- Aminimum of seven years relevant experience in industry.

-- Willhave demonstrated hands-on experience and expertise with Cadence verificationdesign tools or equivalent tools, flows and methodologies required to execute averification project.

-- Willhave demonstrated successful completion of 10+ verification projects as anindividual contributor

-Preferto have DDR IP verification experience