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| Business Title | R&D Engineer, Sr I | | Requisition Number | 5883BR | | Hiring Location(s) | CHINA - Shanghai | | Job Category | Engineering | | Business Unit | Solutions Group | | Hire Type | Employee | | Recruiter | Heather Yang | | Hiring Manager (Reports To) | Jinrong Shao | | Grade | 66 | | Job Description and Requirements | Job Descriptions
1. This position is responsible for IP FPGA prototype work including IP core RTL integration, test bench creation for simulation with Verification IP, FPGA synthesis to achieve clean time result, hardware testing and debugging through hardware instruments.
2. Will be working with the IP core and PHY Design Engineering teams to understand the IP protocols and PHY application, to define and implement the integration architecture.
3. Perform FPGA synthesis, define correct timing constraints, IO constraints to achieve time clean synthesis result
4. Will be involving all states of the prototype development process from the specification define, design implementation, simulation, FPGA synthesis, and hardware system verification.
Position Requirements
1. BSEE or MSEE (is preferable) with 5+ yrs of experiences in FPGA design and IC validation.
2. Must be proficient with Unix OS, Verilog HDL, Perl scripting.
3. Hardware validation and debugging experiences are highly desirable.
4. Knowledge of EDA tools in the areas of Synthesis, Xilinx FPGA implementation flow, Verilog simulation and Verification is plus.
5. Knowledge one of the PCI Express/SATA/USB/HDMI/AMBA Protocol with relevant experience (specifications, compliance and interoperability testing, design/verification experience etc.) will be a definite plus.
6. Has strong desires to learn new technologies and demonstrates good analysis and problem-solving skills
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| Business Title | R&D Engineer, Sr I | | Requisition Number | 6222BR | | Hiring Location(s) | CHINA - Shanghai | | Job Category | Engineering | | Business Unit | Solutions Group | | Hire Type | Employee | | Recruiter | Heather Yang | | Hiring Manager (Reports To) | Jinrong Shao | | Grade | 66 | | Job Description and Requirements | Job Descriptions 1.
This position is responsible for USB protocol FPGA prototype work including IP core RTL integration, test bench creation for simulation with Verification IP, FPGA synthesis to achieve clean time result, hardware testing and debugging through hardware instruments.
2.
Will be working with the IP core, PHY Design Engineering teams and Driver software engineer to understand the IP protocols and PHY application, to define and implement the integration architecture and test plan 3.
Perform FPGA synthesis, define correct timing constraints, IO constraints to achieve time clean synthesis result 4.
Will be involving all states of the prototype development process from the specification define, design implementation, simulation, FPGA synthesis, and hardware system verification. Position Requirements 1.
BSEE or MSEE (is preferable) with 5+ yrs of experiences in FPGA design and IC validation. 2.
Must be proficient with Unix OS, Verilog HDL, Perl scripting. 3.
Hardware validation and debugging experiences are highly desirable. 4.
Knowledge of EDA tools in the areas of Synthesis, Xilinx FPGA implementation flow, Verilog simulation and Verification is plus. 5.
Knowledge of the USB3.0/USB2.0/AMBA Protocol or relevant high speed interface protocol (specifications, compliance and interoperability testing, design/verification experience etc.) will be a definite plus. 6.
Has strong desires to learn new technologies and demonstrates good analysis and problem-solving skills |
| Business Title | R&D Engineer, Sr I | | Requisition Number | 6088BR | | Hiring Location(s) | CHINA - Shanghai | | Job Category | Engineering | | Business Unit | Solutions Group | | Hire Type | Employee | | Recruiter | Heather Yang | | Hiring Manager (Reports To) | Jinrong Shao | | Grade | 66 | | Job Description and Requirements | Job Descriptions 1.
This position is responsible for IP FPGA prototype work including IP core RTL integration, test bench creation for simulation with Verification IP, FPGA synthesis to achieve clean time result, hardware testing and debugging through hardware instruments.
2.
Will be working with the IP core, PHY Design Engineering teams and Driver software engineer to understand the IP protocols and PHY application, to define and implement the integration architecture and test plan 3.
Perform FPGA synthesis, define correct timing constraints, IO constraints to achieve time clean synthesis result 4.
Will be involving all states of the prototype development process from the specification define, design implementation, simulation, FPGA synthesis, and hardware system verification. Position Requirements 1.
BSEE or MSEE (is preferable) with 5+ yrs of experiences in FPGA design and IC validation. 2.
Must be proficient with Unix OS, Verilog HDL, Perl scripting. 3.
Hardware validation and debugging experiences are highly desirable. 4.
Knowledge of EDA tools in the areas of Synthesis, Xilinx FPGA implementation flow, Verilog simulation and Verification is plus. 5.
Knowledge of the USB3.0/USB2.0/AMBA Protocol or relevant high speed interface protocol (specifications, compliance and interoperability testing, design/verification experience etc.) will be a definite plus. 6.
Has strong desires to learn new technologies and demonstrates good analysis and problem-solving skills |
| | Business Title | R&D Engineer, Sr I | | Requisition Number | 6089BR | | Hiring Location(s) | CHINA - Shanghai | | Job Category | Engineering | | Business Unit | Solutions Group | | Hire Type | Employee | | Recruiter | Heather Yang | | Hiring Manager (Reports To) | Jinrong Shao | | Grade | 66 | | Job Description and Requirements | Job Descriptions 1.
This position is responsible for IP FPGA prototype work including IP core RTL integration, test bench creation for simulation with Verification IP, FPGA synthesis to achieve clean time result, hardware testing and debugging through hardware instruments.
2.
Will be working with the IP core, PHY Design Engineering teams and Driver software engineer to understand the IP protocols and PHY application, to define and implement the integration architecture and test plan 3.
Perform FPGA synthesis, define correct timing constraints, IO constraints to achieve time clean synthesis result 4.
Will be involving all states of the prototype development process from the specification define, design implementation, simulation, FPGA synthesis, and hardware system verification. Position Requirements 1.
BSEE or MSEE (is preferable) with 5+ yrs of experiences in FPGA design and IC validation. 2.
Must be proficient with Unix OS, Verilog HDL, Perl scripting. 3.
Hardware validation and debugging experiences are highly desirable. 4.
Knowledge of EDA tools in the areas of Synthesis, Xilinx FPGA implementation flow, Verilog simulation and Verification is plus. 5.
Knowledge of the USB3.0/USB2.0/AMBA Protocol or relevant high speed interface protocol (specifications, compliance and interoperability testing, design/verification experience etc.) will be a definite plus. 6.
Has strong desires to learn new technologies and demonstrates good analysis and problem-solving skills |
| | Business Title | FAE, Sr II | | Requisition Number | 5994BR | | Hiring Location(s) | CHINA - Shanghai | | Job Category | Engineering | | Business Unit | Solutions Group | | Hire Type | Employee | | Recruiter | Heather Yang | | Hiring Manager (Reports To) | Tom Liu | | Grade | 67 | | Job Description and Requirements | A Field Applications Engineer (FAE) is the technical business driver and customer advocate responsible for providing pre-sales technical support for DesignWare STAR Memory System. This position is based in Shanghai but required to support customers across the globe. An FAE’s responsibilities primarily include: 1) Providing direct technical customer support for Synopsys IP products in order to understand customer IP requirements, provide information about Synopsys IP and build strong customer relationships 2) Working with the sales team to be the business driver for IP pre-sales activities within the region 3) Providing status and customer feedback on new/existing requirements for embedded memories and test The FAE builds relationships to customers in order to understand the needs of customers and prospective customers. Once the customer’s needs are understood, the FAE must work across the business unit to gather and provide Synopsys IP information back to the customer. To meet the customer’s needs, the FAE needs a strong working knowledge of ASIC design and the Synopsys IP product information. A good understanding of the process technologies is important.
The FAE provides technical guidance and support to the sales team during the pre-sales process.
Qualified applicants will have a BSEE, MSEE preferred, and 5+ years of SOC test solution experience. Prior FAE experience preferred. An understanding of front-end and/or back-end SOC design flow is important. The ability to conduct technical meetings, presentations, seminars, product demonstrations, and training to customers is required. Experience with embedded memories and memory test is required. This includes in depth knowledge of DFT concept & Experience in MBIST, JTAG, scan insertion, ATPG. Experience in scripting languages such as perl, tcl & experience with industry simulation tools is desirable. Good written and verbal communication skills and problem solving skills are required. The role requires travel (up to 30%). |
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| Business Title | FAE, Staff | | Requisition Number | 5996BR | | Hiring Location(s) | CHINA - Shanghai | | Job Category | Engineering | | Business Unit | Solutions Group | | Hire Type | Employee | | Recruiter | Heather Yang | | Hiring Manager (Reports To) | Tom Liu | | Grade | 68 | | Job Description and Requirements | A Field Applications Engineer (FAE) is the technical business driver and customer advocate responsible for providing pre-sales technical support for Logic Libraries from
the
Synopsys DesignWare Intellectual Property (IP). This position could be based in Shanghai, Shenzhen, or Beijing, and focus on China, but could support world wide if necessary. A logic FAE’s responsibilities primarily include: 1)
Providing direct technical customer support for Synopsys IP products in order to understand customer IP requirements, provide information about Synopsys IP and build strong customer relationships. 2)
Run engagements on cutting edge technology nodes where one has to set up flows and methodologies to show case Synopsys libraries and memory products and to bring out the best in them. 3)
Working with the sales team to be the business driver for IP pre-sales activities within the region. 4)
Providing status & customer feedback on new& existing requirements for the logic library products. Qualified applicants will have a BSEE, MSEE preferred, and 3+ years of SOC design experience. This should include ASIC design with experience using place and route tools. Deep understanding of design methodologies is required, with emphasis placed on the backend physical design process. Knowledge of the front-end design process or experience with Place and Route, Timing signoff, Synthesis, Extraction, and LVS/DRC are plus. Synopsys tool experience is desired, but not required. Excellent verbal and written presentation and communication skills are required. Customer sensitivity, the ability to multiplex many issues & set priorities and have a helpful/caring attitude towards customers, and the desire to assist customers exploit new technologies are essential for success in the position. Good written and verbal communication skills and problem solving skills are required. The role requires travel (up to 30%). |
| Business Title | Corporate Applications Engineer | | Requisition Number | 5129BR | | Hiring Location(s) | CHINA - Shanghai | | Job Category | Engineering | | Business Unit | Solutions Group | | Hire Type | Employee | | Recruiter | Heather Yang | | Hiring Manager (Reports To) | Vince Harradine | | Grade | 67 | | Job Description and Requirements | Description • As a Corporate Applications Engineer (CAE) team in the Solutions Group at Synopsys, you will be responsible for technical support of customers using Synopsys DesignWare DDRn IP. You will analyze and resolve complex IP usage issues and provide timely, accurate technical guidance to customers. You will be interfacing with our Design Engineering team to report on any issues related to the IP’s design, reliability and maintenance or defects. You will have the capability to design and implement solutions to complex application problems independently with little guidance. You will be authoring application-notes and/or white-papers that promote the IP’s ease of use, or address specific challenges in the IP’s usage. You may be called upon to author technical papers and present them in peer-reviewed technical publications or conferences. You will have regular contact with external customers and internal contacts across cross-functional teams. Occasional travel will be required. Requirements • Qualified applicants will have a BSEE, MSEE, + 5 years relevant experience in ASIC design. • Strong communication skills and ability to interact with customers as well as peers is required. • Recent experience with ASIC implementation EDA tools and flows in the areas of Synthesis, Simulation, STA, Verification, Testability, Place and Route, Design Reuse and/or Physical Design is highly desired. • Domain knowledge of the DDR3/2 Protocols with relevant experience is a plus. • Hardware debug and troubleshooting skills are highly desirable. • Relevant experience in design, implementation or technical support with mixed signal designs is highly desired. |
| | Business Title | CAE, Sr I | | Requisition Number | 5208BR | | Hiring Location(s) | CHINA - China | | Job Category | Engineering | | Business Unit | Solutions Group | | Hire Type | Employee | | Recruiter | Heather Yang | | Hiring Manager (Reports To) | Yifei Liu | | Grade | 66 | | Job Description and Requirements |
Job Description and Responsibility: As a member of the Corporate Applications Engineer (CAE) team in the Solutions Group at Synopsys, you will be responsible for technical support of customer using Synopsys IPs. You will be interfacing with our Design Engineering team to report on any issues related to the IP’s design, reliability and maintenance or defects. You will be involved in customer installation, training. You will have the capability to design and implement solutions to complex applications problems independently with little guidance.
You will be authoring application-notes and/or white-papers that promote the IP’s ease of use, or address specific challenges in the IP’s usage
You may be called upon to author technical papers and present them in peer-reviewed technical publications or conferences.
You will have regular contact with external customers and internal contacts across cross-functional teams.
Requirements: Typically requires a minimum of 5 years of related experience. Overall understanding and experience of the ASIC/SoC design process is required. Strong communication skills and ability to interact with customers as well as peers is required. Domain knowledge of the USB, DDR or System Bus Protocol with relevant experience (specifications, compliance and interoperability requirements, design/verification experience etc.) will be a definite plus Knowledge of competitive EDA tool products and product knowledge in any of the areas of Synthesis, Simulation, STA, Verification, Testability, Place and Route, Design Reuse and/or Physical Design is highly desired. Hardware debug and troubleshooting skills are highly desirable. Occasional travel will be required. |
| Business Title | R&D Engineer, Sr I | | Requisition Number | 5738BR | | Hiring Location(s) | CHINA - Shanghai | | Job Category | Engineering | | Business Unit | Solutions Group | | Hire Type | Employee | | Recruiter | Heather Yang | | Hiring Manager (Reports To) | Jasjeet Singh | | Grade | 66 | | Job Description and Requirements | Job Description and Requirements Seeking a highly motivated and innovative digital design and verification engineer with strong theoretical and practical background in high-speed data recovery circuits. Working as part of a highly experienced mixed-signal design team, the candidate will be involved in designing and maintaining current and next generation PCIe, SATA, 10G-KR and USB 2/3 SERDES products. The position offers excellent opportunity to work with an expert team of digital and mixed signal designers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on the test-chips. In addition, this is a great opportunity to work with a wide suite of in-house digital design and verification tools, including VCS, Design Compiler, PrimeTime, LEDA. Job Responsibilities: -
Architecture and RTL coding of high-speed digital circuits, modeling of analog blocks. -
Writing verilog and system-verilog test-benches. Performing functional coverage, assertion coverage, and code coverage. -
Defining place and route constraints, resolving STA issues and performing gate-level simulations. -
Defining and debugging DFT structures in the designs for high DFT coverage. - Managing, reviewing, and tracking the design and verification tasks executed by teams at off-site locations -
Interacting with customer support and back-end design teams. -
Ability to lead and manage small team of engineers This position typically requires BS or MS plus at least 2-4 years of digital design and verification experience in the industry as well as hands on experience in designing high-speed digital circuits, writing complex test-cases in Verilog and System Verilog, and familiarity with code quality metrics. Candidates must have a deep understanding of asynchronous clock crossings, DFT design methodologies, and synthesis implications of RTL. Knowledge of back-end synthesis tools DC/PT is a plus as are good organization and communication skills for interacting between different design groups and customer support teams.
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有兴趣请联系我，terry.hua@synopsys.com |
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发表于 2014-1-10 11:28:27
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