ASIC Manager R&D 武汉

bestgrace · 发表于 2013-12-3 20:00:20

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Position: ASIC Manager R&D [url=mailto:%E7%AE%80%E5%8E%86%E5%8F%91bestgrace@qq.com]简历发bestgrace@qq.com[/url]
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JobPurpose and Mandate:

Thisposition of “Manager II, R&D” is a Mixed-Signal Design Manager focusing onASIC / Digital Design and Verification. In addition to being a manager ofDesign and Verification Engineers, the mandate of this role is to act as aproject lead and technical lead in the design of semiconductor integratedcircuits in compliance with the project’s specifications and Synopsys’ designmethodologies. The successful candidate will work on a variety of design andverification tasks, incorporating such tasks as, and not limited to,architecture definition, specification generation, RTL coding, behaviouralcoding, testbench and testcase generation, RTL simulation, synthesis, STA,gate-level simulation, formal verification, documentation, and prototypeevaluation. As a Manager, the successful candidate will also be responsible forrecruiting, project staffing, project and staff scheduling, performance reviewsand career-path development of staff.

Duties:

• Will be responsible forteam leadership and project leadership.

• Perform staff recruiting,provide staff training, set and monitor staff schedules and goals, and performannual performance reviews of staff.

• Generation of designspecifications.

• Perform architecturestudies for complex digital blocks.

• Write synthesizable RTLcode for circuit portions of integrated circuits.

• Write behavioural models.

• Generate testbenches andtestcases.

• Perform complex RTLsimulations of circuits, interpret the results and optimize the code until thepredetermined functionality is satisfied.

• Generate timing constraintsfor synthesizable designs.

• Perform logic synthesisand/or static timing analysis.

• Perform gate-levelsimulations of circuits, interpret the results and optimize the design untilthe predetermined functionality and timing is satisfied.

• Perform mixed-modesimulations.

• Documentation offunctionality, code, verification environments/plans, and design procedures.

• May participate inprototype evaluation using bench top laboratory instruments or automated testequipment.

• Communicate with otherSynopsys employees regarding customer technical support.

• May communicate directlywith customers regarding technical support.

• Other related duties asassigned by the manager.

Requirements:

• Requires a degree inEngineering or Applied Science (or equivalent) and 5+ years working experiencein a related field.

• Familiarity with verilogcircuit design and design verification.

• Previous staff managementexperience.

• Previous Team and/orProject Leadership experience.

Grace Li @ Hi-Talent ConsultingCo. , Ltd.