Physical Design Manager_Shanghai

qietegong

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The Physical Design Manager will be responsible for the planning and execution of all SoC or IP physical design activities for our clients. She/he will be responsible for execution of Physical Design (place and route) duties both at block level, IP/macro level, as well as chip-level. This includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Logical vs. Schematic (LVS) checks.

The following aspects are desirable:

· Technical

Understanding Verilog HDL;

Understanding Deep Submicron effects such as 180nm and below;

Understanding OCV, DFM, DFY;

Excellent Block level and Full-chip physical design skills;

Background of all aspects of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and Signal Integrity closure, physical verification, low power implementation etc;

Hands on recent or past experience and expertise in Cadence, Synopsys or Mentor Physical Implementation Tools;

Understanding of complete SoC development cycle, from architecture to post-silicon debug preferred;

Should have participated in a minimum of 3 fullchip tapeouts;

· Management

Minimum 2 years of ASIC physical design management experience, working with global teams;

Self-motivated, conflict resolution skills, and experience working with global teams across time zones;

Detail oriented and schedule driven;

People management skills as well as technical project management skills;

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