Nvidia后端部门内推

hbaifenbai

nvidia（上海）后端部门招聘timing相关engineer，以下是职位要求。有意者可发简历到hbaifenbai@126.com

Department: GPU
Location: Shanghai
Job Description/Qualifications:
As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic

• Chip integration and netlist generation
• Synthesis, Formal verification, netlist quality check
• Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
• Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
• Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
• Develop flow to physically partition and floorplan the entire chip.
• Develop scripts for performing ECO's.

Minimum Requirement:

• BS or MS in Electrical Engineering or Computer Science
• Above 3 years of relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closure
• Excellent scripts skills
• Excellent written and verbal communication skills in English
• Ability to multiplex many issues, set priorities, and work in a team environment
• Keep up to date with leading edge technologies

sym0602

b帮我内推下吧，简历已发送。。。。。