【全职】AMD上海研发中心招聘后端工程师及部门经理

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AMD上海研发中心招聘：请感兴趣的务必以“所应聘职位_姓名_学历_工作年限_目前公司”
为标题，把简历以附件形式发送到Maggie1.Zhang@amd.com

1.Sr./MTS/SMTS Physical Design Engineer
Location: Shanghai

Job Responsibility:      
Work with global Front-End design team and physical design team for large scal
e ASIC chip physical implementation. Focus on physical design of deep sub-micr
on GPU chips including block level (full chip) floor planning, timing closure,
place&route, physical verification etc. The individual is expected to be an e
xpert in multiple aspect in PD areas and provide technically leadership to the
engineering team. The individual is also expected to be accountable for proje
ct delivery.

Job Requirements:
•        MSEE with 8+ years or Bachelor with 10+ years of industrial experience
in ASIC design
•        5+ years or more years of experience in physical design of deep submic
ron digital ASIC chips
•        Hands on experience in large scale ASIC chip physical design
•        Knowledgeable in all aspects of deep submicron ASIC design flow
•        Successfully gone through several complete product development cycles
•        Demonstrate strong leadership and work well with cross-functional team
s
•        Good listening, writing and speaking English
•        Good communication skills, strong interpersonal skills and the flexibi
lity
•        Dedicated, hard working and good team player
•        Familiar with Back-End (physical design) EDA tools
•        Familiar with Front-End EDA tools is a plus
•        Familiar with Unix/Linux environment and good at scripts


2.Sect. Manager of Physical Design
Location: Shanghai

Job Responsibility:
Lead a small team of physical engineers to work with global Front-End design t
eam and physical design team for large scale ASIC chip physical implementation
. Focus on physical design of deep sub-micron GPU chips including block level
(full chip) floor planning, timing closure, place&route, physical verification
etc. The individual is expected to be an expert in at least one PD area and p
rovide technically leadership to the engineering team.

Job Requirements:
•        MSEE with 5+ years or Bachelor with 8+ years of industrial experience
in ASIC design
•        3+ years or more years of experience in physical design of deep submic
ron digital ASIC chips
•        Hands on experience in large scale ASIC chip physical design
•        Knowledgeable in all aspects of deep submicron ASIC design flow
•        Successfully gone through several complete product development cycles
•        Demonstrate leadership and work well with cross-functional teams
•        Good listening, writing and speaking English
•        Good communication skills, strong interpersonal skills and the flexibi
lity
•        Dedicated, hard working and good team player
•        Familiar with Back-End (physical design) EDA tools
•        Familiar with Front-End EDA tools is a plus
•        Familiar with Unix/Linux environment and good at scripts