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Responsible for WS and/or Final Test program development for ASIC devices including probe card and loadboard board designs and performance in a production environment.
Leading first silicon debug. Will lead high speed test strategy, working closely with the design group to develop optimum solutions for production test.
Work with design and DFT engineer to define test coverage & methodology and Support development of test plan.
Be responsible for test time reduction and test program maintenance & optimization in production.
Cooperate with product engineer for yield enhancement and the customer return analysis.
Has implemented SCAN/TDF, and memory BIST.
Has implemented complex functional tests.
Has worked on high speed/at speed test for complex interfaces such as SERDES, PCI express, USB3.0 and optical interfaces etc.
Has worked on Mixed-signal testing (ADC/DAC Dynamic and Linearity tests).
Minimum of 3 years experience on Verigy 93K and/or Teradyne’s J750, Flex and Ultra-Flex. Other platforms’ experience as a plus. Solid background on ATE testing, test methodology, Silicon process, high speed digital and Mixed-signal testing.
BSEE/MSEE degree, or equivalent, and 5+ years experience in Wafer Sort and Final Test of complex, multi-functional IC products.
Fluent in Visual basic, C++, PERL programming languages.
Good interpersonal and communication skills required.
KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.
If you interested in the job, pls sent your cv to: hr@kthr.com, thanks! |
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