【上海&北京】知名美资500强公司诚聘IC工程师

helena_eb

以下职位是热招的，真实有效^^，流程很快～薪水45w之内都可以谈

Job Title:	Staff Design Verification Engineer for Graphics  Hardware
City/Town:	Shanghai
Country:	China
Job Description:	Key Job Functions:   - Understand the architecture of the chip and functional block being designed   - Compose test plan and validation vectors to ensure functional completeness   - Develop verification environments for standalone unit testing and  enhance/use the automated regression infrastructure setup for unit level, IP  level and full chip functional verification.   - Help debug and correct functional errors in the design blocks, using logic  abstraction, simulation and debug tools, based on good understanding of the  architectural specification, RTL and/or device level design of the block.   - Closely working with Design/Architecture/Circuit team to identify the  Milestones and Quality metrics of the project that includes scoping, tracking  and delivery.   - Be responsible to mentor and coach the team for greater technical depth in  Functional areas as well as the verification methodology improvement and  Infrastructure enhancements to support the design environment      Preferred Experience:   - Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+  years working experiences   - Should be versatile in any one of the high level verification flow such as  SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for  verification   - Needs to have better understanding of Verification methodology and  concepts.   - Should have good understanding of Pre-Silicon design process from  Architecture, Design, Synthesis and Gate level Implementation till Tapeout  release.   - Should have excellent communication skills (both written and oral) and  should be able to participate cross functional engineering teams  geographically.   - Familiar with Linux Environment (including shell scripting and linux gnu  tools)   - Advanced programming knowledge on Verilog,C++   - Design for verification (assertion based design strategies, code coverage,  functional coverage, test plan, gate-level simulation, back-annotation etc.)   - Strong problem solving skills

Member oftechnical staff for IC design verification (MTS DV)

Requirements:

The candidate is preferred to be MSEE with minimum of 6years, or BSEEwith
minimum of 8 years experience in digitalASIC/SOC design verification.  

The candidate must have:

1.
deep understanding on ASIC/SOC designflow

2.
Excellent knowledge of design verification methodology,such as VMM or OVM.

3.
Solid experiences with
simulation model creation and thetestbench build

4.
Strong RTL coding with Verilog

5.
Strong C/C++ software developmentexperiences

6.
Begood at scripting language, such as Perl, C shell, Makefile.

It is amust that the candidate has one or more of the followingexperience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus,USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash hostcontroller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design,clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs(SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet,JTAG, etc.

The candidate is expected to exhibit goodverbal and written communication skills in both Chinese and English, specializedknowledge plus broad technical knowledge that facilitates integrative thinking,, driving execution of quality and timely result, capability  to solve complex, novel and no-recurring problemsand decision-making on critical technical areas

Hands-on lab experience is another plus, ableto understand and/or use the use scopes, logic analyzers, has knowledge or skillof board-level lab debugging.

Responsibility:

The successful candidate will work with teammembers and apply current functional verification techniques to perform andimprove pre-silicon verification quality and product Time to Market forSouthbridge design. The candidate will provide the technical leadership to theDV team for the new Southbridge project. He/She should be able to workindependently on various DV tasks and providing technical guidance to the DVteam. The candidate would involve technically in the porting/creation of the DVenvironment for the new design, block and chip level test plan creation andimplementation, coverage analysis, and regression cleanup.

上海的职位在张江，北京的职位在中关村～
感兴趣的朋友请发CV到helena.bri@hotmail.com，或加msn聊聊～

伽偌

研究生在，顶一下

ksj116

新年顶一贴，期待更多的招聘信息

greg_chang

感觉比较对口哦，过段时间不知道还有没有。对第二个感兴趣。