求学

zhaojie657

这是设计源文件
library ieee;
use ieee.std_logic_1164.all;
entity shifter_ent is
port(data: in std_logic_vector(3 downto 0);
     load,clk,enable : in std_logic;
     mode:in std_logic_vector(1 downto 0);
     output: out std_logic_vector(3 downto 0));
end shifter_ent;
architecture shifter_arch of shifter_ent is
signal internal_output : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clk='1' and clk'event) then
  if(enable='0') then
    if(load='0') then
      internal_output<=data;
    else
    case mode is
    when "00" => internal_output<=internal_output(2 downto 0) & '0';
    when "01" => internal_output<='0' & internal_output(3 downto 1);
    when "11" => internal_output<=internal_output(2 downto 0) &internal_output(3);
    when "10" => internal_output<=internal_output(0) &internal_output(3 downto 1);
    when others => internal_output<="0000";
    end case;
    end if;
  else
   internal_output<="0000";
  end if;
end if;
end process;
output<=internal_output;
end shifter_arch;


-----------------------------------------------------  这是测试平台
library ieee;
use ieee.std_logic_1164.all;
package shifter_package is
constant cycle : time :=50 ns ;
signal sig_data : std_logic_vector(3 downto 0);
signal sig_mode : std_logic_vector(1 downto 0);
signal sig_output_before_shifter : std_logic_vector(3 downto 0);
signal sig_output_after_shifter : std_logic_vector(3 downto 0);
procedure load_data(
  signal load : out std_logic;
  signal data : out std_logic_vector(3 downto 0);
  signal mode : out std_logic_vector(1 downto 0));
procedure check_data(
  signal mode : out std_logic_vector(1 downto 0));
end shifter_package;
package body shifter_package is
procedure check_data (
  signal mode : out std_logic_vector(1 downto 0)) is
begin
  mode<=sig_mode;
  if(sig_mode="00") then
     if(sig_output_after_shifter/=sig_output_before_shifter(2 downto 0)&'0') then
     assert false
     report"Error detected in shift left"
     severity warning;
     end if;
elsif(sig_mode="01")then
     if(sig_output_after_shifter/='0'&sig_output_before_shifter(3 downto 1)) then
      assert false
      report"Error detected in shift right"
      severity warning;
     end if;
elsif(sig_mode= "10")then
      if(sig_output_after_shifter/=sig_output_before_shifter(0)&sig_output_before_shifter(3 downto 1)) then
        assert false
        report"Error detected in shift barrel right "
        severity warning;
     end if;
  elsif(sig_mode= "11" ) then
      if(sig_output_after_shifter/=sig_output_before_shifter(2 downto 0)&sig_output_before_shifter(3 )) then
        assert false
        report "Error detected in shift barrel left"
        severity warning;
      end if;
   end if;
end check_data;
procedure load_data(
    signal data: out std_logic_vector(3 downto 0);
    signal mode : out std_logic_vector(1 downto 0);
    signal load : out std_logic) is
begin
data<=sig_data;
mode<=sig_mode;
load<='1';
wait for cycle ;
load<='0';
wait for cycle;
load<='1';
wait for cycle;
end  load_data;
end  shifter_package;

-----------------------------------------------------------------------------
LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY shifter_ent_vhd_tst IS
END shifter_ent_vhd_tst;
ARCHITECTURE shifter_ent_arch OF shifter_ent_vhd_tst IS
-- constants                                                
-- signals                                                   
SIGNAL clk : STD_LOGIC;
SIGNAL data : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL enable : STD_LOGIC;
SIGNAL load : STD_LOGIC;
SIGNAL mode : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL output : STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT shifter_ent
        PORT (
        clk : IN STD_LOGIC;
        data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        enable : IN STD_LOGIC;
        load : IN STD_LOGIC;
        mode : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
        );
END COMPONENT;
BEGIN
        i1 : shifter_ent
        PORT MAP (
-- list connections between master ports and signals
        clk => clk,
        data => data,
        enable => enable,
        load => load,
        mode => mode,
        output => output
        );
clk<= not clk after cycle/2;                                 
always : PROCESS                                             
-- optional sensitivity list                                 
-- (        )                                                
-- variable declarations                                      
BEGIN  
enable<='0';  --启动移位器
-------------------------------------------------------------
sig_data<="1010"; ----将数据“1010”载入移位器
sig_mode<="00";
wait for cycle;
load_data(load,data,mode);
------------------------------------------------------
for i in 0 to 6 loop    --左移
sig_output_before_shifter<=output;
wait for cycle;
sig_output_after_shifter<=output;
wait for cycle;
check_data(mode);
end loop;
-----------------------------------
sig_data<="1010"; ----将数据“1010”载入移位器
sig_mode<="01";
wait for cycle;
load_data(load,data,mode);
--------------------------------------
for i in 0 to 6 loop    --右移
sig_output_before_shifter<=output;
wait for cycle;
sig_output_after_shifter<=output;
wait for cycle;
check_data(mode);
end loop;
                                                                                         
        -- code executes for every event on sensitivity list  
WAIT;                                                        
END PROCESS always;                                          
END shifter_ent_arch;
这个设计在quartus中是对的，测试平台在quartus自动调用modelsim出现了错误，我不知道这是为什么，向各位好友求教。
错误为： ** Error: E:/exercise/x/simulation/modelsim/shifter_ent.vhd(61): Procedure "load_data" declared at line 9 has no body.
# ** Error: E:/exercise/x/simulation/modelsim/shifter_ent.vhd(61): VHDL Compiler exiting
# ** Error: E:/modelsim.altera/modelsim_ae/win32aloem/vcom failed.

jpyangyyq

头好晕啊
那么多

duqiang290

是FPGA的程序吧，，