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Job Title: Senior design verification methodology engineer
Location: Beijing
Job description:
1. Setup advanced ASIC design verification methodology/working flow.
2. Apply advanced verification methodology to complex module/sub-system verification.
3. Keep in touch with EDA vendors to keep the leading position of design verification methodology.
4. Company common verification infrastructure setup and maintain.
Requirement:
1. Ms Degree in Microelectronics/Electrical Engineering/Computer Science.
2. Minimum 1 years of ASIC design/verification experience.
3. Familiar with one of Contraint Random Verification(CRV) methodologies - VMM/OVM/UVM.
4. Familiar with perl and tcl script.
5. Familiar with SOC architecture and AMBA specification is a plus.
6. Experience of one of the following field is highly preferred.
-> Complex VIP development with VMM/OVM/UVM.
-> Low power verification techniques
-> SystemC design verification and SC/SV co-simulation.
-> Hardware acceleration technique.
-> Complex IP verification experience, like PCIE,USB3.
Please send your resume to tao.liu@mediatek.com if you're interested. |
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