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Abstract—As technology scales, the shrinking wire width
increases the interconnect resistivity, while the decreasing interconnect
spacing significantly increases the coupling capacitance.
This paper proposes reducing the number of bus lines of the
conventional parallel-line bus (PLB) architecture by multiplexing
each m-bits onto a single line. This bus architecture, the serial-link
bus (SLB), transforms an n-bit conventional PLB into an n/m-line
(serial link) bus. The advantage of SLBs is that they have fewer
lines, and if the bus width is kept the same, SLBs will have a larger
line pitch. Increasing the line width has a twofold reduction effect
on the line resistance; as the resistivity of sub-100 nm wires drops
significantly, the line width increases. Also, increasing the line
width and spacing reduces the coupling capacitance between adjacent
lines, but increases the line-to-ground capacitance. Thus, an
optimum degree of multiplexing 􀀀 and an optimum width to
pitch ratio 􀀀 exist, which minimizes the bus energy dissipation
and maximizes the bus throughput per unit area. The optimum
degree of multiplexing and optimum width-to-pitch ratio for maximum
throughput per unit area and minimum energy dissipation
for the 25–130-nm technologies was determined in this paper.
Also, an encoding technique was proposed and implemented to
reduce the switch activity penalty due to serialization. HSPICE
simulations show that for the same throughput per unit area
as conventional parallel-line data buses, the SLB architecture
reduces the energy dissipation by up to 31% for a 64-bit bus implemented
in an intermediate metal layer of a 50-nm technology,
and a reduction of 53% is projected for a 25-nm technology.
Serial-Link Bus A Low-Power On-Chip Bus Architecture.pdf
(1.09 MB, 下载次数: 77 )
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