经典IC设计面试问题6

yanzhang98

What         is difference between Verilog full case and parallel case?

A         "full" case statement is a case statement in which all possible         case-expression binary patterns can be matched to a case item or to a         case default. If a case statement does not include a case default and if         it is possible to find a binary case expression that does not match any         of the defined case items, the case statement is not "full."
A         "parallel" case statement is a case statement in which it is only         possible to match a case expression to one and only one case item. If it         is possible to find a case expression that would match more than one         case item, the matching case items are called "overlapping" case items         and the case statement is not "parallel."

微尘770021

参考下。。。。。