Atheros招聘网络处理芯片工程师

forer

公司名称 Atheros （NYSE: ATHR) www.atheros.com
地点 上海张江
方向 MACsec/IPsec/其他网络安全标准的开发,入职后提供RSU及Option
联系信箱 Cheng.Yan@Atheros.com
Job Overview:
As an ASIC design engineer, you will have the opportunities to apply your extensive hardware experience in designing and validating Network protocol processor. You will be working closely with software engineer and system engineer to develop and implement leading Network Security SoC.

Responsibilities include:  Design and Verification, Synthesis, formal verification and timing closure, Chip debug and verification, FPGA emulation & debug, C/C++ modeling for firmware and hardware verification, IP development and support.

Qualifications:

1. BS in Electrical/Electronics Engineering, MS preferred.
2. 1~3 years experience with various network/security protocol process is required, especially in FPGA/chip implementation of those protocols.
3. One or more advantages as following are highly desirable: Familar with NIST/IETF/IEEE standards; Experiences with C/C++ develop in RHEL.

Skills/Experience:

1. Strong background and experience required in C/C++, Verilog, tcl and matlab.
2. Must be proficient in IC design simulation, synthesis.
3. Experience in FPGA debug and P&R flow.

vinber

请问有实习的机会吗，小弟现在在张江，已经发了CV到您邮箱，谢谢！

wangjunweiair