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本帖最后由 fusionlux 于 2010-3-26 00:42 编辑
内部推荐AMD上海研发中心诸多急招职位，有兴趣有实力者可联系我fusionlux@gmail.com，合适的话我帮你内部推荐，大家一起Win With AMD。
MTS Physical Design Engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION: Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical 1. PhD with 3+ years of industrial experience or MSEE with 5+ years of industrial experience in ASIC design 2. Experience on hierarchical design from chip level to block level. 3. Expertise in place and routing, signal integrity, power analysis, CTS design, DFT, design rule and connectivity verification, timing closure. 4. Successfully gone through complete product development cycle. Good analytical and 5. Good listening, writing and speaking English. 6. Good communication skills, strong interpersonal skills and the flexibility. Dedicated, hard working and good team player 7. Familiar with Back-End (physical design) EDA tools (synopsys, cadence, magma) 8. Familiar with Front-End EDA tools or circuit design is a plus 9. Familiar with Unix/Linux environment and good at scripts DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION: 1. Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design 2. Build test bench and monitors for DUT 3. Debug function/performance bugs of relative memory control blocks 1. MS or above of EE or related fields. 2. A solid foundation of Computer Architecture or DDR feature or memory controller 3. At least 5 years work experience on Design. 4. Proficient on Verilog and asic design flow 5. Familiar with Perl or other script language Staff/ Sr. GPU ASIC Integration Engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION - Responsible for the execution of the chip integration process. This will include design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design. - Responsible for synthesis, netlist generation, timing and logical equivalency checks, and timing constraint management. In this role you will get to experience many aspects of the chip design process working as the bridge between the logic design & verification group and the physical design group. Every piece of the design that will make it into the final chip will at some point pass through your virtual hands. 1. Master Degree in electrical engineering with 4+ years of digital circuit design and logic design experience; Or Bachelor Degree with 7+ years related working 2. Familiar with Verilog HDL coding and ASIC Frond-End flow 3. Familiar with unix/linux and scripts (tcl, perl etc.) 4. Strong task-based organization skill 5. Computer Architecture and computer Arithmatic 6. Computer Graphic Basic knowledge(a plus) 7. DDR-SDRAM/PCI/PCI-e experience(a plus) Staff ASIC Verification Engineer___Display DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION - Responsible for display IP development and maintenance - Responsible for IP level synthesis/formal check - Work with verification engineer on IP level validation - Work with front-end integration team and physical design team on timing closure - Communication with driver team to build driver - Bachelor with 5+ yeas and Master with 3+ in Electrical or Computer Engineering. - Strong RTL coding and familiar with front-end design flow - Experience on synthesis, timing analysis and formal verification. - Experience of Video/Graphics post-processor(scaling/composition/gamma/deinterlace) - Experience of display specific-interconnection protocols (DisplayPort, LVDS, VGA,HDCP, DVI, HDMI etc) is a plus. - Good at C/C++, Perl, familiar with SystemC, PLI, Makefile is a plus - Design for verification (assertion based design strategies, code coverage, functional coverage, test plan etc.) - Good communication skills and fluent English. - Strong responsibilities and team spirit. Staff ASIC/Layout Design Engineer__PCIe DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION - Participate IP and SoC level architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures. - Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage. - Go through the FE design flow to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan. - Write ASIC specific part of test plan. Co-work with verification engineers to prove functional correctness from block level to SoC level - Support FW/SW bring-up and debugging - Working as the technical point of contact on the ASIC area. - Maintain design environment, solve flow issues, and develop scripts to improve flow - Proven ASIC / SoC Design Experience (5+ years as a bachelor, 3+ years as a master). - Must have strong background on IP development - Must be proficient in Verilog coding, debugging and modeling - Must be skilled in ASIC design flow, such as synthesis, DFT, timing analysis, ECO - Must be skilled in mainstream EDA tools for design and simulation such as ncsim/vcs, RC/DC, PT, Formality/LEC and DFT. - Must be familiar with verification methodologies for from block level to SoC level. - Should be familiar with shell/perl/tcl programming in linux OS. - Should be familiar with P&R and Manufacture tech. - Good English hearing, speaking, reading and writing capabilities. - Will be a big plus if having mass production tape‐out experience. - Will be a plus if having C/C++/SystemVerilog experience Staff ASIC/Layout Design Engineer__South Bridge DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION : The AMD South Bridges Group has openings for a MTS/Sr. Design Verification Engineer. The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for Southbridge design. He/She should be able to work independently on various DV tasks and providing technical guidences to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level testplan creation and implementation, coverage analysis, and regression - MSEE,BSEE or equivalent degree, - Minimum of 3 years of ASIC design verification experience. - Knowledge of design verification methodologies. - Some of the peripheral I/O interfaces, such as PCIE, USB, SATA,PCI, SD, JTAG or - Shell/perl/Makefile programming in linux OS. - Verilog design/simulation and SystemC/C++ programming - Hardware assertion languages such as PSL/SVA, - Test bench creation and functional coverage with HDL's such as System Verilog or -
Good verbal and written communication skills in both Chinese and English. DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION : We are currently looking for an Senior Eng Design Verification Engineer who will be responsible for all aspects of verification on next generation integrated processors chipset, including developing DV infrastructure environment, testbenches, modeling, assertions/checkers/monitors, test plan & test development, regressions, and infrastructure development. Responsibility includes participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy: - Verification of Graphic North Bridge design using complex DV environment C/C++, SystemVeilog, OVM, SystemC, Verilog - Infrastructure development - Experience in use of front end CAD tools Synopsys (VCS, ) - Strong documentation and communication skills. - Ability to work well in a dynamic, fast-paced, pressure filled, multiple sites North - Flexible in terms of responsibilities and hours. - Bachelor/Master in Electrical/Computer Engineering. - Strong C and C++ software development and scripting languages (Perl, C Shell, - Good knowledge of SystemVerilog and OVM is desirable. - 3+ years experience in Verification in a large scale ASIC design environment. - Strong background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA). - Strong analytical thinking skills, excellent attention to detail, and good coding skills - Must be organized, enthusiastic self-starter and have good communication skills and the ability and desire to work as a team. MTS. SOC ASIC CAD engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION - Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with AMD - Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge graphics processing - Technical support and programming - Interface with EDA venders on technology - major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years - good programming skill with one or more languages (eg, tcl, perl , python, c/c++, etc) in unix/linux and a strong desire to automate flow - experience in ASIC design (digital design, Front-end or Back-end,) - familiar with one or more ASIC flows (logic synthesis, STA, formality check, Design for Power ) and usage of related EDA tools - Good written and spoken English - Good communication skills and be able to work both independently and in a team Sr. SOC ASIC CAD engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION - Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with AMD - Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge graphics processing - Technical support and programming - Interface with EDA venders on technology - major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years - good programming skill with one or more languages (eg, tcl, perl , python, c/c++, etc) in unix/linux and a strong desire to automate flow - experience in ASIC design (digital design, Front-end or Back-end,) - familiar with one or more ASIC flows (logic synthesis, STA, formality check, Design for Power ) and usage of related EDA tools - Good written and spoken English - Good communication skills and be able to work both independently and in a team Front-end ASIC Design CAD Engineer for Graphics Hardware DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION - Understand the FE ASIC design flow, design verification flow, and integration flow. - Consolidate the design and verification methodologies for graphics and microprocessor - Develop infrastructure and release for variant IP/SOC teams. - Explore the advanced design and verification methodologies for high efficient R&D. - Good written and fluent oral English - Graduates from Electrical Engineering (EE) or Computer Science (CS) - Master with 2+ working experience, or Bachelor with 3+ working experience - Familiar with Linux Environment (including shell scripting and linux gnu tools) - Scripting language experience a plus (perl, ruby, tcl, etc.) - Experience with design verification methodologies (plus) 􀂄
2+ year experience on Verilog HDL coding and debugging 􀂄
1+ year experience on c/c++ 􀂄
Familiar with SystemVerilog 􀂄
3+ year experience on c/c++ 􀂄
1+ year experience on Verilog HDL coding and debugging (plus) 􀂄
Familiar with SystemVerilog or SystemC (plus) MTS Design Engineer__Southbridge DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION: The AMD South Bridges Group has an opening for MTS Design Engineer familiar with USB technology. The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for USB host controllers in Southbridge. The role will include working on the following tasks from time to time, specification, HDL coding, synthesis, timing closure, etc. The job may require some lab bringup and debugging of our reference PC system after the Southbridge chip comes back. 1. The successful candidate will have a MSEE,BSEE or equivalent degree. 2. Must have minimum of 5+ years of ASIC design experience, proficient in RTL(verilog), experienced with top level integration tasks, familiar with simulation, 3. The candidate must have the experience/knowledge of USB 1.1/2.0 and 4. It is preferred the candidate is familiar with USB 3.0 and xHCI. 5. The candidate must exhibit good verbal and written communication skills in both 6. Hands-on lab experience is a plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of PC system lab debugging. Sr. Eng DV Engineer__Fusion DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION: We are currently looking for Senior Eng Design Verification Engineers who will be responsible for all aspects of verification on next generation integrated processors (CPU + GPU + Multi Media) chipset, including developing testbenches, modeling, assertions/checkers/monitors, test plan & test development, regressions, and infrastructure development. Responsibility includes participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy: - Verification of Graphic North Bridge design using random methodologies – Test Planning, Implementation and Execution. - Develop System Verilog (OVM) random sequences and methods. - Maintain and Interface with existing random generators, models and APIs - Integration of random modules to various testbenches. - Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause. - Strong documentation and communication skills. - Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites - Flexible in terms of responsibilities and hours. - Bachelor/Master in Electrical/Computer Engineering. - 4+ years experience in complex ASIC/SOC Design Verification, direct experience in SOC or Processor (GPU or CPU) or Industry bus standard (PCI-e, MC, HT) or multimedia/video is preferred. - Good knowledge of SystemVerilog and OVM. - Good knowledge of Verilog/C/C++/System C/SystemVerilog. - 2+ years experience in Verification. - Verification insights into random techniques. - Verification of large scale ASICs. - Working knowledge of x86 assembly programming is an asset. - Experience in power verification is an asset. - Verification of Virtualization Components is an asset. - Strong C and C++ software development and scripting languages (Perl, C Shell, - Strong background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA). - Strong analytical thinking skills, excellent attention to detail, and good coding skills - Must be organized, enthusiastic self-starter and have good communication skills and the ability and desire to work as a team. Senior Program Manager – GPU Solutions Engineering DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION: The individual who fills this role will be responsible for driving programs from inception to full deployment. This individual will lead cross-functional product development core teams, aligning all aspects of engineering and operation execution to meet business goals. This individual will interact with AMD executives and senior management team, 3rdparty partners, and possibly customers. This individual will be responsible for the management of program execution and its day-to-day activities centered around GPU development, post-silicon validation, and pre-production ramp. This individual will work with engineering management to drive execution excellence, including key metrics like Time-to-Market, Time-to-Yield, and Silicon Quality Indicators. This individual will work collaboratively with the AMD Program Management community on infrastructure development and continuous process improvement. Work is strategic and tactical in nature with execution excellence being a key priority. Communication is a critical part of this role which includes interpreting/understanding business directions, explaining tactical details, and recommending solutions regarding complex program situations. The job may lead to more supervisory roles, and working directly with executives. Travel is - BS in EE (or equivalent). Masters in EE or Engineering/Operations Management (or - Experience in managing large, complex, interrelated projects, programs, and functions to aggressive deadlines. - Experience in large scale ASIC development, including definition, integration, physical design, and design verification. - Working knowledge across multiple engineering disciplines (i.e. Boards, Thermal, Packaging, Process Technology, Product Engineering, Software) is desirable. - Experience in Operations, Product Marketing, and/or Product Management is a plus. - Ten years minimum related experience with five years (plus) management experience - Experience with programs that can change quickly and may be speculative in nature. - Results driven, disciplined, and analytical. - Good problem solving skills, interpersonal skills, communications skills, and | 
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发表于 2010-3-13 10:19:59
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