FPGA Design Engineer, Shenzhen

jingli888ca

Location:Shenzhen

Title: FPGA Design Engineer

Report:Hardware manager

Education:BSEE, BSCE, BECS, required, MSEE, MSCE, MSCS preferred

Year ofexperiences: 3 years full time in FPGA / ASIC development and logic design experiencerequired; 5+ years preferred
Detailedtechnical know-how:

1). RTL proficiency, VHDL andVerilog are required, system verilog is an asset; expected to have goodunderstanding physical entities described in RTL, able to come up with newmicro-architecture based on technical specification;

2). Familiar with Xilinx and Alteratools, should have multiple cycles of development experiences, including fromconcept, specification, high level architecture and low level architecture,coding, verification, emulation, board debugging;

3). Familiar with simulators, suchas ModelSim, vcs, verilog-xl or nc-verilog, etc.

4). Familiar scripting languages,such as perl and csh;

5). Familiar with version controlsystems, such as cvs, and able to merge codes from different branches;

6). Have good verification skills,able to create test plan, design test bench, and write test cases, both atmodule level and at the chip level;

7). Have SoC prototypingexperiences, familiar with MIPS or ARM cores, familiar with internal systembuses, such as AMBA (AXI, AHB, APB) protocols, have insight on AMBAconfiguration.

8). Familiar with memory generators,such as Artisan memory generator, FPGA core gen / memory compiler, able tobuild single-port, 2-port, dual-port, register file based on various needs, andable to align the different timing properly;

9). Familiar with core tools, suchas coreAssembler;

10). Solid working skills withoscilloscope, logic analyzer, good with board debugging, such as basic issueswith power, clock, reset, data bus, etc. Also able to review hardware schematics from the FPGA developmentperspective;

11). Good spoken English and writtenEnglish, able to talk over phone and write clear technical documents;

12). Synthesis skill, such as usingDC, is an asset;

13). 3G knowledge preferred, such asFEC concept and algorithm, etc.

Contact: jingli888ca@yahoo.com

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