几个基于FPGA的DSP设计窍门(Tips for DSP design)

haichao

Tip #1
Start at the beginning.
Complex DSP designs start with an algorithm developer who creates the initial
design based on existing designs and experience. According to the DSP market
research firm Forward Concepts, the leading tool for algorithm design is MATLAB from MathWorks. Using the MATLAB language, algorithm developers can create
designs in a natural and productive form and may tap into an immense wealth of
designs, scripts, and engineering knowhow available only in the MATLAB
language. Though designers can choose from other options including blocklevel
environments, such as Simulink or SPW, or languages based on C/C++,
these environments are less widely used and there may not be as many designs
available for them. Moreover, many constructs used in DSP designs – such as
looping, repeated structures, and 2- or 3- dimensional data arrays – are much easier to represent in MATLAB than in blocklevel environments. Once the algorithmis created in MATLAB, it can be readily shared or partitioned across a design team and reused over time.

Tip #2
Avoid recopying your work (or alternatively, “Don’t get lost in translation”).
Once the algorithm is available, the rest of the design team, including hardware
designers, software developers, and system designers who integrated the design
components, swings into motion. In the past, the completed algorithm in MATLAB
became the executable specification, which meant that the hardware designer
and software developers needed to recreate the design.
Many embedded systems developers are accustomed to implementing DSP
algorithms on general purpose DSPs in C or assembly language. This puts hardware
and software engineers into the role of translating designs from one language to
another, creating many opportunities for inserting errors with the attendant debugging process. To avoid this process altogether, companies are looking to architectural synthesis tools that use the MATLAB M-file as the golden source for downstream design, automatically synthesizing the design at the Register Transfer Level (RTL). Coupled with traditional RTL synthesis tools that can synthesize RTL to gate-level implementation, this establishes an unbroken design flow from algorithmic creation to hardware implementation.

Tip #3
Always check your work – use a verification flow that is complete.
In any design process, it’s essential to be able to verify that the design meets the higher level specifications. If the design starts as a floating-point algorithm in MATLAB – also called an M-file – the fixed-point M-file should behave within an acceptable range of the floating-point M-file. The RTL implementation should then conform precisely to the fixed-point M-file – in other words, the RTL should be bit-true to the floating-point M-file. But how does the engineer determine that the design matches all the way through? The proven method for verifying designs in top-down flows is via a testbench that feeds the design under test with its input stimulus and monitors whether its outputs match the expected results. Designers should create testbenches that allow this methodology to be employed using HDL simulators, but better yet, they should seek out tools that automatically generate an RTL testbench from the original design and use an HDL simulator to simulate and functionally verify the design including bit-true operation.

Tip #4
Don’t reinvent the wheel.
DSP systems incorporate a number of building blocks that are common to most
designs – FIR and IIR filters, fast Fourier transforms and discrete cosine transforms, channel coding, etc. Developing these functions from scratch comes at great expense; in fact, according to Berkeley Design Technology, Inc., developing a new FFT in silicon can consume up to six months. Designers need to adopt tools and techniques that provide access to a large and growing variety of DSP intellectual property (IP) that is geared towards DSP design. While there are many sources for IP in hard form (laid out on target silicon) or in soft form (delivered in synthesizeable RTL), typically there is no corresponding simulation model available in MATLAB. This breaks the verification flow, making it difficult for the algorithm developer
and the hardware designer to validate that the algorithm is faithfully represented in silicon.


Tip #5
Use your budget wisely.
DSP algorithms are almost always developed using floating-point arithmetic,
giving the algorithm developer the ability to evaluate a design in its best case
scenario. While general-purpose DSPs are typically designed to perform 16- or 32-bit arithmetic, implementing algorithms in FPGAs or ASICs gives the designer the ability to independently control the number of bits used to represent each number in the algorithm. Using too many bits can be costly – a 40% increase in the number of bits in a multiplier can double its area in silicon – but using too few can lead to overflows or instabilities. When choosing tools for implementing DSP algorithms in silicon, designers should evaluate tools that help automate this floating-point to fixedpoint conversion process.

Tip #6
Given the time, you can always make a design better – use design exploration.
Almost invariably, getting the functionality of the design correct is just the beginning – then begins the pursuit of improving performance to make specs and trying to shrink to a smaller device or go to a slower speed grade to cut costs. Hardware engineers have an arsenal of tools and tricks at their disposal, but working at gate-level – even at RTL level – has its limits. Inserting intermediate registers can be difficult. Optimizing quantization throughout a design is particularly tedious and error-prone when changing at the RTL level. And, if the algorithm developer comes up with a brilliant new idea two weeks into the hardware design, chances are that the project manager will decide to stick with the old design rather than risk the entire project schedule. The greatest benefits can be realized by keeping the original floating-point MATLAB source file as the golden source for all design and using algorithmic synthesis tools that synthesize from MATLAB to RTL. Using architectural synthesis tools such as AccelChip DSP Synthesis, the algorithm designer can make changes to the design well into the flow, resynthesize to RTL, and work with the hardware designer to determine whether the design performance and device utilization has improved.

tmchrry

不错

marui139980

斑竹的英语太厉害了，实在羡慕的很。而且有这么强的专业知识，目标呀

55555

谢谢了。。

frank123

几个基于FPGA的DSP设计窍门(Tips for DSP design)

thanks

yang0203

谢谢了。。