I think it mitigates the positive feedback from output node sensing to internal bias current. Usually the transient enhanced design has positive feedback loops. You can insert 'stb' into powerMOS' gate terminal to analyze the phase margin with or without the resistors.
/1 
eetop公众号
创芯大讲堂
创芯人才网
IP卡
狗仔卡
发表于 
提升卡
沉默卡
喧嚣卡
变色卡
创芯人才网