This an interesting and really useful paper on linearising differential pair.
Years ago in an 0.28u bicmos process I used the same front end even though the client wanted a switched capacitor design which I though linearised differential pair more feasable at 10Mbit
This operates at Gbit in 22nm finfet technology, hope it helps somebody.
Linearity Analysis of Source-DegeneratedDifferential Pairs for Wireline Applications: