日志
【转】modelsim无法识别include文件的解决方法
| |
只写成 `include "define_file.v" 是不行的，要使用绝对路径，如 `include "F:/110503_Test/rtl/define_file.v"。
详情如下：
详情如下：
QUESTION:
From Xilinx ISE I get the following error:
ERROR:hdlCompilers:26 - "rtl/definitions.v" line 2 expecting 'EOF',
found 'parameter'
When I compile in ModelSim I get the following error:
** Error: D:/rtl/rf_board_top.v(23): Cannot open `include file
"definitions.v".
How to get ModelSim to find the include file (it is in the same
directory as the verilog modules)?
ANSWER:
I moved the `include after the port definitions and that fixed ISE
problem.
I changed the properties on each .V source file to include the
directory where the include file was located (even though it was the
same directory as the source .v files). This fixed the ModelSim
problem.
/1 
eetop公众号
创芯大讲堂
创芯人才网