Springer2010年PLL书：60-GHz CMOS Phase-Locked Loops

hsh22

60-GHz CMOS Phase-Locked Loops
Hammad M. Cheema l Reza Mahmoudi Arthur H. M. van Roermund


1 Introduction ................................................................ 1
2 Synthesizer System Architecture ......................................... 11
2.1 IEEE 802.15.3c Channelization ....................................... 13
2.2 60 GHz Frequency Conversion Techniques . . . ........................ 14
2.3 Proposed PLL Architecture: Flexible, Reusable,
Multi-frequency ........................................................ 17
2.3.1 Utilization in WiComm Project ................................ 18
2.4 System Analysis and Design .......................................... 18
2.4.1 Phase-Lock Loop Basics ........................................ 19
2.4.2 Frequency Planning ............................................. 21
2.4.3 Synthesizer Parameters ......................................... 22
2.5 System Simulations .................................................... 28
2.6 Target Specifications .................................................. 32
2.7 Summary ............................................................... 33
3 layout and Measurements at mm-Wave Frequencies ................. 35
3.1 Layout Problems and Solutions ....................................... 36
3.1.1 Impact of Parasitics ............................................. 37
3.1.2 Mismatch Due to Layout Asymmetry
and Device Orientation ......................................... 41
3.1.3 Substrate Losses ................................................ 42
3.1.4 Cross Talk Shielding and Grounding . . . ........................ 44
3.2 Measurement Setups ................................................... 48
3.2.1 Dedicated Instrumentation ...................................... 49
3.2.2 Calibration and De-embedding ................................. 51
3.2.3 Stability and Repeatability ..................................... 54
3.3 Conclusions ............................................................ 55
4 Design of High Frequency Components ................................. 57
4.1 Prescaler ............................................................... 59
4.1.1 Overview and Comparison of Prescaler Architectures ......... 60
4.1.2 35 GHz Static Frequency Divider .............................. 69
4.1.3 40 GHz Divide-by-2 ILFD ..................................... 78
4.1.4 60 GHz Divide-by-3 ILFD ..................................... 88
4.1.5 Monolithic Transformer Design and Measurement ............ 95
4.1.6 Dual-Mode (Divide-by-2 and Divide-by-3) ILFD ............. 97
4.1.7 ILFD figure-of-Merit (FOM) .................................. 104
4.1.8 Summary ....................................................... 106
4.2 Voltage Controlled Oscillator ........................................ 106
4.2.1 Overview of VCO Architectures .............................. 107
4.2.2 Theoretical Analysis of LC-VCOs ............................ 111
4.2.3 40 GHz LC VCO .............................................. 115
4.2.4 60 GHz Actively Coupled I-Q VCO . . . ....................... 123
4.2.5 60 GHz Transformer Coupled I-Q VCO ...................... 129
4.2.6 Dual-Band VCO for 40 and 60 GHz . . . ....................... 137
4.3 Synthesizer Front-Ends ............................................... 140
4.3.1 40 GHz VCO and Divide-by-2 ILFD . . ....................... 141
4.3.2 60 GHz VCO and Divide-by-3 ILFD . . ....................... 146
4.4 Conclusions ........................................................... 148
5 Design of Low Frequency Components ................................ 151
5.1 Feedback Division .................................................... 152
5.1.1 CML Based Divider Chain .................................... 152
5.1.2 Mixer Based Division ......................................... 157
5.2 Phase-Frequency Detector, Charge-Pump and Loop Filter .......... 160
5.3 Conclusions ........................................................... 164
6 Synthesizer Integration .................................................. 165
6.1 Synthesizer for 60 GHz Sliding-IF Frequency Conversion .......... 166
6.1.1 Comparison to Target Specifications . . . ....................... 174
6.2 Synthesizer with Down-Conversion Mixer in Feedback Loop ...... 175
6.3 Dual-Mode Synthesizer ............................................... 177
6.4 Conclusions ........................................................... 180
7 Conclusions ............................................................... 183
Appendix ...................................................................... 185
Appendix A . . .............................................................. 185
A Travelling Wave Divider Simulation Results .......................... 185
Appendix B . . .............................................................. 186
B LC-VCOs Theory ....................................................... 186
References .................................................................... 191


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tanguaner

好东西，先收藏了

kevin_hmy

回复 1# hsh22


   谢谢，楼主厚道a

risccpu

thanks.

qchunh

正在做锁相环谢了

ysliu168

Thanks!

chlliu

谢谢共享，顶一个。

jansenchen

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linyuanfei

感谢楼主的共享

sdm01

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