Handbook of VLSI Routing Techniques - Serial and Parallel Models

KongDu

1 INTRODUCTION
1.1 Sequential routing models
1.2 Parallel routing models
1.3 Organization

2 MAZE ROUTING ALGORITHMS
2.1 Maze routing
2.2 Variants of maze routing
2.3 Parallel maze routing
2.4 Case Study: A custom VLSI design for concurrent maze routing
2.5 Line-probe routing

3 GLOBAL ROUTING ALGORITHMS
3.1 Global routing
3.2 Global routing graphs and region ordering
3.3 Sequential global routers
3.4 Concurrent approaches to global routing
3.5 Parallel global routing algorithms
3.6 Global routing for Analog designs
3.7 Case Study: A complete global routing system for SOG designs

4 CHANNEL ROUTING ALGORITHMS
4.1 Introduction
4.2 Left edge Algorithm(LEA)and its variants
4.3 Doglegged channel routers
4.4 Multi-Layer Channel Routers
4.5 Gridless approaches
4.6 Specialized channel routers
4.7 Parallel channel routing
4.8 Case Study (MARS):A detailed gridless general area router

5 SWITCHBOX ROUTING ALGORITHMS
5.1 Switchbox routing
5.2 Parallel switchbox routing algorithms
5.3 Case Study:A parallel multi-layer detailed routing framework

6 SPECIALIZED AND TECHNOLOGY-SPECIFIC ROUTING ALGORITHMS
6.1 Power and ground routing
6.2 Timing driven routing
6.3 Single-row routing for PCBs
6.4 Routing algorithms for FPGAs
6.5 Routing for MCM designs
6.6 Case Study:High Performance Interconnect Design and Analysis

7 CONCLUSION
7.1 Commercial Tools
7.2 Academic layout Systems

REFERENCES

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