在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 3978|回复: 5

[求助] 网表中有时钟分屏的DFT应该如何处理

[复制链接]
发表于 2019-12-10 16:06:50 | 显示全部楼层 |阅读模式
100资产
网表中存在时钟分屏,做DFT_drc检查时有如下告警,X25995这4500多个的SDFF都是接在分屏时钟上的,且生成的扫描链只有几十个SDFF,其他分屏时钟上的SDFF的SI和SE都接地了。
如果在create_test_protocol前增加命令set_dft_configuration -fix_clock enable,虽然也有如下的告警,但是最终生成的扫描链上所有的SDFF都在了,但是现在问题来了,插入扫描链后,仿真时序不满足了,我应该怎么解决?
Warning: Clock input CK of DFF X25995 was not controlled. (D1-1)
Information: There are 4505 other cells with the same violation. (TEST-171)
Warning: Set input SDN of DFF X24253 was not controlled. (D2-1)
Information: There are 51 other cells with the same violation. (TEST-171)
Warning: Reset input RDN of DFF X20054 was not controlled. (D3-1)
Information: There are 5428 other cells with the same violation. (TEST-171)
Warning: Clock input CK of DFF X11055 not active when clocks are set on. (D9-1)
Information: There are 1086 other cells with the same violation. (TEST-171)
Warning: Clock D2088 connects to data input (D) of DFF i_DIGFUNG_BLK/X20019. (D10-1)
Information: There are 20 other cells with the same violation. (TEST-171)
Warning: Clock T2001 can capture new data on TE input CK of DFF i_I2C_REG_BLK/X311. (D14-1)
         Source of violation: input CK of DFF i_I2C_REG_BLK/X20355.
Information: There are 7 other cells with the same violation. (TEST-171)
Warning: R3000 clock path affected by new capture on LS input RDN of DFF i_DIGFUNG_BLK/X21131. (D15-1)
         Source of violation: input RDN of DFF i_I2C_REG_BLK/X20366.
Information: There are 19 other cells with the same violation. (TEST-171)


这是我插扫描链的脚本:
source -echo -verbose ./script/dc_setup.tcl
read_file -format ddc results/DIG_ALL.mapped.ddc
current_design DIG_ALL
link

set_app_var test_default_delay 0
set_app_var test_default_bidir_delay 0
set_app_var test_default_strobe 40
set_app_var test_default_period 100
set_dft_signal -view existing_dft -type ScanClock -port SCAN_CLK -timing [list 16.7 33.3]
set_dft_signal -view existing_dft -type Reset -port Rest -active_state 1
set_dft_signal -view existing_dft -type TestMode -port TEST_MODE -active_state 1

set_dft_signal -view spec -type ScanEnable -port SCAN_SE -active_state 1
set_dft_signal -view spec -type ScanDataIn -port SCAN_IN
set_dft_signal -view spec -type ScanDataOut -port SCAN_OUT
set_dft_signal -view spec -type TestData -port SCAN_CLK
set_dft_signal -view spec -type TestData -port Rest


set_dft_configuration -fix_clock enable -fix_set enable -fix_reset enable -fix_bus enable
set_scan_configuration -chain_count 1 -clock_mixing mix_clocks
set_scan_path -view spec c0 -scan_data_in SCAN_IN -scan_data_out SCAN_OUT -scan_enable SCAN_SE
create_test_protocol -infer_clock
dft_drc
set_dft_insertion_configuration -synthesis none -preserve_design_name true
preview_dft -test_points all > ./autofix.pts
insert_dft

report_scan_path > ${RESULTS_DIR}/scan.scanpath
write_sdf ${RESULTS_DIR}/${DESIGN_NAME}.scan.sdf
write_sdc -nosplit ${RESULTS_DIR}/${DESIGN_NAME}.scan.sdc
write -f verilog -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.scan.v


最佳答案

查看完整内容

add those command after this statement if you still want to use AutoFix future : set_dft_configuration -fix_clock enable -fix_set enable -fix_reset enable -fix_bus enable # For clock D1 set_autofix_configuration -type clock -method mux -control_signal TEST_MODE - test_signal SCAN_CLK # For set/reset D2/D3 set_autofix_configuration -type reset -method mux -control_signal TEST_MODE - test_signal ...
发表于 2019-12-10 16:06:51 | 显示全部楼层
add those command after this statement if you still want to use AutoFix future :

set_dft_configuration -fix_clock enable -fix_set enable -fix_reset enable -fix_bus enable

# For clock  D1
set_autofix_configuration -type clock -method mux -control_signal TEST_MODE - test_signal SCAN_CLK
# For set/reset  D2/D3
set_autofix_configuration -type reset -method mux -control_signal TEST_MODE - test_signal Reset
....

insert_dft
 楼主| 发表于 2019-12-12 08:39:32 | 显示全部楼层


ngohongtiep 发表于 2019-12-11 17:12
add those command after this statement if you still want to use AutoFix future :

set_dft_configurat ...


貌似D1/D2/D3的告警没有了,现在还有另外2个问题请教一下:
1、如何让扫描链按照总线从低到高的路径(D[0]->D[1]->D[2]....)这样的方式生成?
2、由于I/O口少,因此设计上想通过I2C配置某几组寄存器来开启和关闭测试模式,因此这几组寄存器是不能加入扫描链的,应该如何配置才能让这几组寄存器不加入扫描链中?


发表于 2019-12-23 11:00:20 | 显示全部楼层
学习了
发表于 2019-12-31 10:22:54 | 显示全部楼层


vectorli 发表于 2019-12-12 08:39
貌似D1/D2/D3的告警没有了,现在还有另外2个问题请教一下:
1、如何让扫描链按照总线从低到高的路径(D[ ...


1.我用过set_scan_path -head_elements -tail_elements来指定instance的顺序,你这个reg的顺序应该也是这个命令,自己man下尝试下
2.首先set_scan_configuration -exclude_elements {inst_i2c}可以让inset_i2c不插扫描链;然后在set_auto_fix_configuration -type clock/set/reset时,也要记得加-exclude_elements {inst_i2c},防止auto_fix时也去动到inst_i2c




我最近做到的一个dft也是i2c配置来置scan_mode为1,来省一个端口,后面tmax跑的时候,也是一大堆坑,spf文件要复现i2c配置scan_mode为1的时序,你有没联系方式,加个好友,讨论下怎么弄这种情况
发表于 2019-12-31 10:28:14 | 显示全部楼层
再搭车问一下,dft auto_fix时钟时,在func_clk和dft_clk的root端一进来就加了mux了,mux的S端也由scan_mode控制了,为啥后面func_clock的ICG后,ICG输出时钟ECLK又来一遍跟dft_clk mux,导致func_clk被拉长好多,后面时钟树平衡也不好做,有啥办法控制不让ICG后的时钟ECLK跟dft_clk添加mux
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

小黑屋| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-3-29 07:18 , Processed in 0.023474 second(s), 7 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表